Towards Diagrammability and Efficiency in Event Sequence Languages

Abstract

Abstract. Many industrial verification teams are developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardware specific, as well as efficient to verify. While the formal verification community has formal models for assessing the efficiency of an event sequence language, none of these models also accounts for designer friendliness. We propose an intermediate language for event sequences that addresses both concerns. The language achieves usability through a correlation to timing diagrams; its efficiency arises from its mapping into deterministic weak automata. We present the language, relate it to existing event sequence languages, and prove its relationship to deterministic weak automata. These results indicate that timing diagrams can become more expressive while remaining more efficient for symbolic model checking than LTL.

Automated Synthesis of Assertion Monitors using Visual Specifications

“…There have been efforts on formalizing other visual notations such as timing diagrams [6,15]. But compared to CESC, these are limited in capability for specifying the complex event behaviors such as causality relationships, repetitive event sequences and multiple clocked synchronizations that are commonly found in SoC design context.…”

“…Precise and unambiguous specification is central to the success of system design and verification. Capturing high-level assertions using specification languages such as PSL/Sugar [5] or temporal logic becomes complex for interactions involving long event sequences [6]. On the other hand, manual construction of assertion monitors using native languages is error-prone and does not scale well.…”