Towards Efficient SpMV on Sunway Manycore Architectures

Liu, Changxi; Xie, Bin; Liu, Xin; Xue, Wei; Yang, Hailong; Liu, Xu

doi:10.1145/3205289.3205313

Cited by 43 publications

(22 citation statements)

References 26 publications

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“…CSTF (Blanco et al 2018) proposes a novel queuing strategy to exploit the data reuse between the computation procedures in CP decomposition that reduces the communication cost significantly. In the meanwhile, there are surging research works (Zhong et al 2018;Liu et al 2018;Hu et al 2019;Liu et al 2019;Han et al 2019;Chen et al 2018;Li et al 2018a, b;Duan et al 2018) based on Sunway architecture in the past few years, which provide valuable experience to our work. The achievable performance by leveraging the architecture features of Sunway such as memory architecture, CPEs and register communication, is quantitatively measured by Xu et al (2017) with both memory-bound and computing-bound benchmarks.…”

Section: Related Workmentioning

confidence: 99%

“…swMR (Zhong et al 2018), a MapReduce programming framework based on Sunway architecture, leverages the computing resources of Sunway processor to automatically parallelize the map/reduce processing and optimize the performance using the unique architectural features such as CPEs and register communication. A sparse matrix vector multiplication algorithm optimized for Sunway architecture, is proposed by Liu et al (2018). The proposed technique optimizes the sparse matrix vector multiplication by tiling resource and data into three levels, and then leverage register communication and local device memory to implement effective data transfer and better usage of CPEs.…”

Section: Related Workmentioning

confidence: 99%

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swTensor: accelerating tensor decomposition on Sunway architecture

et al. 2019

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Modern applications are digesting and generating data with rich features that are stored in high dimensional array or tensor. The computation applied to tensor, such as Canonical Polyadic decomposition (CP decomposition) plays an important role in understanding the internal relationships within the data. Using CP decomposition to analyze large tensor with billions of sizes requires tremendous computation power. In the meanwhile, the emerging Sunway many-core processor has demonstrated its computation advantage in powering the first hundred petaFLOPS supercomputer in the world. In this paper, we propose swTensor that adapts the CP decomposition to Sunway processor by leveraging the MapReduce framework for automatic parallelization and the unique architecture of Sunway for high performance. Specifically, we divide the major computation of CP decomposition into four sub-procedures and implement each using MapReduce framework with customized design key-value pair. Also, we tile the data during the computation so that it fits into the limited local device memory on Sunway for better performance. Moreover, we propose a performance auto-tuning mechanism to search for the optimal parameter settings in swTensor. The experimental results demonstrate swTensor achieves better performance than the state-of-the-art BigTensor and CSTF with the average speedup of 1.36 × and 1.24 × , respectively. Besides, swTensor exhibits better scalability when scaling across multiple Sunway processors.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

swTensor: accelerating tensor decomposition on Sunway architecture

et al. 2019

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“…For each CDP, it enumerates the sample-NMO velocity pairs (line 2), and then nds the intersection of the traveltime curve and traces. At each intersection, it rst obtains the halfpoint of the current trace (line 9-11), then accesses the data with size of w (line 12-13), and nally retrieves the data computed in a window of width w (line [14][15][16][17][18][19]. Each trace has its own corresponding halfpoints, therefore the accesses to halfpoints are continuous when walking through the traces sequentially.…”

Section: Improving Parallelism Within a Cgmentioning

confidence: 99%

“…For the current trace, the memory addresses of the data accesses are calculated for each sample-NMO velocity pair and kept in the k1 array (line [13][14][15]. en, the maximum and minimum memory address in k1 array is identi ed (line [16][17][18] and used to determine the memory range (len th) of data accesses (line 19). e data within the memory range is copied to LDM at one time through DMA operation (line 20).…”

Section: 32mentioning

confidence: 99%

“…Especially, the atmospheric dynamics [22] and earth-quake simulation [7] running on the full system of Sunway TaihuLight for large-scale computation won the ACM Gordon Bell prize. Moreover, the optimization of various computation kernels, such as SpMV [16] and stencil [1], also demonstrates the unique performance advantage of Sunway architecture. In addition to the traditional scienti c applications, the Sunway processor has also shown its potential to support emerging applications.…”

Section: Introductionmentioning

confidence: 99%

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Massively Scaling Seismic Processing on Sunway TaihuLight Supercomputer

Yang

Luan

et al. 2020

IEEE Trans. Parallel Distrib. Syst.

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Common Midpoint (CMP) and Common Re ection Surface (CRS) are widely used methods for improving the signal-to-noise ratio in the eld of seismic processing. ese methods are computationally intensive and require high performance computing. is paper optimizes these methods on the Sunway many-core architecture and implements large-scale seismic processing on the Sunway Taihulight supercomputer. We propose the following three optimization techniques: 1) we propose a so ware cache method to reduce the overhead of memory accesses, and share data among CPEs via the register communication; 2) we re-design the semblance calculation procedure to further reduce the overhead of memory accesses; 3) we propose a vectorization method to improve the performance when processing the small volume of data within short loops. e experimental results show that our implementations of CMP and CRS methods on Sunway achieve 3.50× and 3.01× speedup on average compared to the-state-of-the-art implementations on CPU. In addition, our implementation is capable to run on more than one million cores of Sunway TaihuLight with good scalability.

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swGBDT: Efficient Gradient Boosted Decision Tree on Sunway Many-Core Processor

Yin

Dun

et al. 2020

Supercomputing Frontiers

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Towards Efficient SpMV on Sunway Manycore Architectures

Cited by 43 publications

References 26 publications

swTensor: accelerating tensor decomposition on Sunway architecture

swTensor: accelerating tensor decomposition on Sunway architecture

Massively Scaling Seismic Processing on Sunway TaihuLight Supercomputer

swGBDT: Efficient Gradient Boosted Decision Tree on Sunway Many-Core Processor

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