Towards Formal Approaches to System Resilience

Sharma, Vishal; Haran, Arvind; Rakamarić, Zvonimir; Gopalakrishnan, Ganesh

doi:10.1109/prdc.2013.14

Cited by 57 publications

(26 citation statements)

References 26 publications

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“…Researchers have also explored the development of application-level error detectors for detecting soft-error affecting a program's control states [14]- [16]. Another key area in application-level resilience is the algorithm based fault tolerance (ABFT) which exploits the algorithmic properties of well-known applications to derive efficient error detectors [17], [18].…”

Section: Background and Related Workmentioning

confidence: 99%

PRESAGE: Protecting Structured Address Generation against Soft Errors

Sharma

Gopalakrishnan

Krishnamoorthy

2016

2016 IEEE 23rd International Conference on High Performance Computing (HiPC)

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Abstract-Modern computer scaling trends in pursuit of larger component counts and power efficiency have, unfortunately, lead to less reliable hardware and consequently soft errors escaping into application data ("silent data corruptions"). Techniques to enhance system resilience hinge on the availability of efficient error detectors that have high detection rates, low false positive rates, and lower computational overhead. Unfortunately, efficient detectors to detect faults during address generation (to index large arrays) have not been widely researched. We present a novel lightweight compiler-driven technique called PRESAGE for detecting bit-flips affecting structured address computations. A key insight underlying PRESAGE is that any address computation scheme that flows an already incurred error is better than a scheme that corrupts one particular array access but otherwise (falsely) appears to compute perfectly. Enabling the flow of errors allows one to situate detectors at loop exit points, and helps turn silent corruptions into easily detectable error situations. Our experiments using PolyBench benchmark suite indicate that PRESAGE-based error detectors have a high error-detection rate while incurring low overheads.

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Section: Background and Related Workmentioning

confidence: 99%

PRESAGE: Protecting Structured Address Generation against Soft Errors

Sharma

Gopalakrishnan

Krishnamoorthy

2016

2016 IEEE 23rd International Conference on High Performance Computing (HiPC)

Self Cite

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“…LLVM already comprises two projects aimed at developing LLVM based fault injectors: (i) LLFI [66,67] and (ii) KULFI [68].…”

Section: Llvm Based Fault Injectormentioning

confidence: 99%

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Vallero

Tselonis

Foutris

et al. 2015

Microprocessors and Microsystems

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International audienceAdvanced computing systems realized in forthcoming technologies hold the promise of a significant increase of computational capabilities. However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable. Developing new methods to evaluate the reliability of these systems in an early design stage has the potential to save costs, produce optimized designs and have a positive impact on the product time-to-market

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“…However, on the subject of using fault injection technologies to study application vulnerability there has been some related work [17,14].…”

Section: Related Workmentioning

confidence: 99%

Empirical Studies of the Soft Error Susceptibility ofSorting Algorithms to Statistical Fault Injection

Guan

DeBardeleben

Blanchard

et al. 2015

Proceedings of the 5th Workshop on Fault Tolerance for HPC at eXtreme Scale

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Soft errors are becoming an important issue in computing systems. Near-threshold voltage (NTV), reduced circuit sizes, high performance computing (HPC), and high altitude computing all present interesting challenges in this area. Much of the existing literature has focused on hardware techniques to mitigate and measure soft errors at the hardware level. Instead, in this paper we explore the soft error susceptibility of three common sorting algorithms at the software layer. We focus on the comparison operator and use our software fault injection tool to place faults with fine precision during the execution of these algorithms. We explore how the algorithm susceptibilities vary based on input and bit position and relate these faults back to the source code to study how algorithmic decisions impact the reliability of the codes. Finally, we look at the question of the number of fault injections required for statistical significance. Using standard practice equations used in hardware fault injection experiments we calculate the number of injections that should be required to achieve confidence in our results. Then we show, empirically, that more fault injections are required before we gain confidence in our experiments.

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Towards Formal Approaches to System Resilience

Cited by 57 publications

References 26 publications

PRESAGE: Protecting Structured Address Generation against Soft Errors

PRESAGE: Protecting Structured Address Generation against Soft Errors

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Empirical Studies of the Soft Error Susceptibility ofSorting Algorithms to Statistical Fault Injection

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