Towards Hardware Support for Common Sensor Processing Tasks

Gupte, Adwait; Jones, Phillip H.

doi:10.1109/rtcsa.2009.16

Cited by 2 publications

(4 citation statements)

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“…The SPU prototype used less than .5% of the resouces available, and was tightly coupled to the Power PC processor embedded into this family of FPGA. Gupte and Jones [2009] give further details on some of the specifics of this platform. As indicated in Section 7, a future direction for this work is to couple the SPU with the PID coprocessor on the RAVI platform.…”

Section: Development Platformsmentioning

confidence: 99%

“…At the heart of our approach is a time-multiplexed hardware PID controller and a Sensor Processing Unit (SPU) [Gupte and Jones 2009] that are tightly integrated with an embedded processor as functional units. The architecture provides deterministic response times on the order of microseconds with low jitter, and can scale to support hundreds of PID control loops.…”

Section: Introductionmentioning

confidence: 99%

“…The primary contributions of this work are: (1) the tight integration of a time-multiplexed hardware PID controller within an embedded processor, (2) the characterization of our PID controller architecture and several alternative hardware/ software hybrid-designs with respect to response time and jitter, (3) the tight integration of a hardware-based Sensor Processing Unit (SPU) within an embedded processor and its evaluation with respect to software implementation of common sensor processing tasks in terms of response time [Gupte and Jones 2009]. …”

Section: Introductionmentioning

confidence: 99%

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Hardware architectural support for control systems and sensor processing

Vyas

Gupte

Gill

et al. 2013

ACM Trans. Embed. Comput. Syst.

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The field of modern control theory and the systems used to implement these controls have shown rapid development over the last 50 years. It was often the case that those developing control algorithms could assume the computing medium was solely dedicated to the task of controlling a plant, for example, the control algorithm being implemented in software on a dedicated Digital Signal Processor (DSP), or implemented in hardware using a simple dedicated Programmable Logic Device (PLD). As time progressed, the drive to place more system functionality in a single component (reducing power, cost, and increasing reliability) has made this assumption less often true. Thus, it has been pointed out by some experts in the field of control theory (e.g., Astrom) that those developing control algorithms must take into account the effects of running their algorithms on systems that will be shared with other tasks. One aspect of the work presented in this article is a hardware architecture that allows control developers to maintain this simplifying assumption. We focus specifically on the Proportional-Integral-Derivative (PID) controller. An on-chip coprocessor has been implemented that can scale to support servicing hundreds of plants, while maintaining microsecond-level response times, tight deterministic control loop timing, and allowing the main processor to service noncontrol tasks.In order to control a plant, the controller needs information about the plant's state. Typically this information is obtained from sensors with which the plant has been instrumented. There are a number of common computations that may be performed on this sensor data before being presented to the controller (e.g., averaging and thresholding). Thus in addition to supporting PID algorithms, we have developed a Sensor Processing Unit (SPU) that off-loads these common sensor processing tasks from the main processor.We have prototyped our ideas using Field Programmable Gate Array (FPGA) technology. Through our experimental results, we show our PID execution unit gives orders of magnitude improvement in response time when servicing many plants, as compared to a standard general software implementation. We also show that the SPU scales much better than a general software implementation. In addition, these execution units allow the simplifying assumption of dedicated computing medium to hold for control algorithm development.

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Section: Development Platformsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hardware architectural support for control systems and sensor processing

Vyas

Gupte

Gill

et al. 2013

ACM Trans. Embed. Comput. Syst.

Self Cite

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show abstract

“…Additionally, our hardware enforced mitigation of non-determinism simplifies software development and verification, since a real-time scheduling scheme is not needed for sharing the computing medium between real-time and non-real-time tasks. Section 4.3 provides a detailed overview of our architecture.Contributions The primary contributions of this work are 1) the tight integration of a time multiplexed hardware PID controller within an embedded processor, 2) the characterization of our PID controller architecture and several alternative hardware/software hybrid-designs with respect to response time and jitter, 3) the tight integration of a hardware-based sensor processing unit (SPU) within an embedded processor and its evaluation with respect to software implementation of common sensor processing tasks in terms of response time[47].…”

mentioning

confidence: 99%

Design exploration of hardware accelerators for mitigating the effects of computational delay on digital control loops

Vyas

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Towards Hardware Support for Common Sensor Processing Tasks

Cited by 2 publications

References 8 publications

Hardware architectural support for control systems and sensor processing

Hardware architectural support for control systems and sensor processing

Design exploration of hardware accelerators for mitigating the effects of computational delay on digital control loops

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