Towards Low-Cost Mechanisms to Enable Restoration of Encrypted Non-Volatile Memories

Ye, Mao; Zubair, Kazi Abu; Mohaisen, Aziz; Awad, Amro

doi:10.1109/tdsc.2019.2941193

Cited by 9 publications

(13 citation statements)

References 31 publications

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“…It introduces a counter write coalescing scheme and a cross-bank counter storage to decrease the number and the execution time of write requests, respectively. More effort towards low-overhead encrypted NVMs is presented in Osiris [54], a new memory controller design that provides crash consistency for encryption counters. The number of NVM writes is reduced by eliminating the unnecessary evictions from the counter cache, which waives significant performance overheads.…”

Section: Related Workmentioning

confidence: 99%

“…Compiler-support for Critical Data Persistence in NVM54:Pseudo code of the compiler pass code analysis and generation.Input: Loop L in LLVM IR // Innermost loop of the loop-nest tagged by the custom pragma directive isTiled, isPartial // Compile time commandline options targetLoopInductionVariable, targetArrayName[[from:to,]from:to] // Pragma arguments, optional range limits Output: Updated Loop L with necessary flushing one-level (LC flush ) or two-level (LR flush and LC flush ) loop-structure and logging/synchronization instructions for persisting data TargetArray ← get pointer to targetArrayName CLELEMENTS ← Cache line size / sizeOf( * TargetArray) // No. of array elements per cache line N ← Number of elements per row in TargetArray childLoop ← L currentLoop ← L.getParentLoop() // outermostLoop.getDepth() = 1 while currentLoop.getDepth() > 0 do if currentLoop.inductionVariable is targetLoopInductionVariable then codeInsertionPoint ← after last instruction of currentLoop if optionalRangeProvided then fill LR flush .LowerBound, LR flush .UpperBound, LC flush .LowerBound, and LC flush .UpperBound end if isTiled then LR flush ← newLoop() // loop to iterate over multiple rows to be flushed; ex.…”

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confidence: 99%

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Compiler-support for Critical Data Persistence in NVM

Elkhouly

Alshboul

Hayashi

et al. 2019

ACM Trans. Archit. Code Optim.

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Non-volatile Main Memories (NVMs) offer a promising way to preserve data persistence and enable computation recovery in case of failure. While the use of NVMs can significantly reduce the overhead of failure recovery, which is the case with High-Performance Computing (HPC) kernels, rewriting existing programs or writing new applications for NVMs is non-trivial. In this article, we present a compiler-support that automatically inserts complex instructions into kernels to achieve NVM data-persistence based on a simple programmer directive. Unlike checkpointing techniques that store the whole system state, our technique only persists user-designated objects as well as some parameters required for safe recovery such as loop induction variables. Also, our technique can reduce the number of data transfer operations, because our compiler coalesces consecutive memory-persisting operations into a single memory transaction per cache line when possible. Our compiler-support is implemented in the LLVM tool-chain and introduces the necessary modifications to loop-intensive computational kernels (e.g., TMM, LU, Gauss, and FFT) to force data persistence. The experiments show that our proposed compiler-support outperforms the most recent checkpointing techniques while its performance overheads are insignificant. CCS Concepts: • Software and its engineering → Source code generation; Runtime environments; Main memory; • Hardware → Emerging languages and compilers;

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Section: Related Workmentioning

confidence: 99%

mentioning

confidence: 99%

Compiler-support for Critical Data Persistence in NVM

Elkhouly

Alshboul

Hayashi

et al. 2019

ACM Trans. Archit. Code Optim.

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“…In this work, we assume a similar threat mode as in state-of-the-art work in secure memory architecture [5,7,8,22,27,28,30,31,33]. The trust base is limited to the processor and its internal structures.…”

Section: Threat Modelmentioning

confidence: 99%

“…Each memory pool implements its own media controller that translates Gen-Z commands into media-specific read and write operations. Processing elements must use the Gen-Z coupled with security features i.e, encryption and integrity verification [5,7,8,30,31,33,34]. While the secure memory implementations are not limited to NVMs due to similar data remanance attacks performed in DRAM i.e., cold boot attack [32], our work is not limited to NVMs as well.…”

Section: Introductionmentioning

confidence: 99%

“…Typically, security metadata caches are used to reduce the required memory accesses for encryption/decryption and integrity verification [19]. Previous work in secure memory architecture [7,[28][29][30][31]33] considered a system that has a single memory pool protected by a single Merkle-Tree. However, each node in the FAM architecture has an access to a private local memory, and a global shared memory.…”

Section: Introductionmentioning

confidence: 99%

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Caching Techniques for Security Metadata in Integrity-Protected Fabric-Attached Memories

Alwadi¹,

Awad²

2018

ICST Transactions on Security and Safety

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The constant need for larger memories and the diversity of workloads have drove the system vendors away from the conventional processor-centric architecture into a memory-centric architecture. Memorycentric architecture, allows multiple computing nodes to connect to a huge shared memory pool and access it directly. To improve the performance, each node uses a small local memory to cache the data. These architectures introduce several problems when memory encryption and integrity verification are implemented. For instance, using a single integrity tree to protect both memories can introduce unnecessary overheads. Therefore, we propose Split-Tree, which implements a separate integrity tree for each memory. Later, we analyze the system performance, and the security metadata caches behavior when separate trees are used. We use the gathered insights to improve the security metadata caching for the separate trees and ultimately improve the system performance.

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Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks

Deligiannis¹,

Cantoro

Reorda

et al. 2021

IEEE Access

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Nowadays, many electronic systems store valuable Intellectual Property (IP) information inside Non-Volatile Memories (NVMs). Designers widely use encryption mechanisms to enhance the integrity of such IPs and protect them from any unauthorized access or modification. At the same time, often such IPs are critical from a reliability standpoint. Thus, dedicated techniques are employed to detect possible reliability threats (e.g., transient faults affecting the NVM content). The weights of a neural network (NN) model (e.g., integrated into an object detection system for autonomous driving or robotics) are typical examples of precious IP items. Indeed, NN weights often constitute proprietary data, stemming from an extensive and costly training process; moreover, their correctness is key for the NN to work reliably. In this article, we explore the capability of encryption mechanisms to ensure protection from both reliability threats. In particular, we assess, via extensive fault injection campaigns, the capability of different memory encryption schemes -usually used only for security purposes -to detect faults and thus, enhance the reliability of the system. Experimental results show that by cleverly choosing the proper encryption scheme, it is possible to achieve very high fault detection rates (greater than 99%) with respect to Multiple Bit Upsets. The gathered results pave the way to the integration of reliability and security mechanisms to achieve better results with lower costs.

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Towards Low-Cost Mechanisms to Enable Restoration of Encrypted Non-Volatile Memories

Cited by 9 publications

References 31 publications

Compiler-support for Critical Data Persistence in NVM

Compiler-support for Critical Data Persistence in NVM

Caching Techniques for Security Metadata in Integrity-Protected Fabric-Attached Memories

Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks

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