Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks

Abstract

Nowadays, many electronic systems store valuable Intellectual Property (IP) information inside Non-Volatile Memories (NVMs). Designers widely use encryption mechanisms to enhance the integrity of such IPs and protect them from any unauthorized access or modification. At the same time, often such IPs are critical from a reliability standpoint. Thus, dedicated techniques are employed to detect possible reliability threats (e.g., transient faults affecting the NVM content). The weights of a neural network (NN) model (e.g., integrated into an object detection system for autonomous driving or robotics) are typical examples of precious IP items. Indeed, NN weights often constitute proprietary data, stemming from an extensive and costly training process; moreover, their correctness is key for the NN to work reliably. In this article, we explore the capability of encryption mechanisms to ensure protection from both reliability threats. In particular, we assess, via extensive fault injection campaigns, the capability of different memory encryption schemes -usually used only for security purposes -to detect faults and thus, enhance the reliability of the system. Experimental results show that by cleverly choosing the proper encryption scheme, it is possible to achieve very high fault detection rates (greater than 99%) with respect to Multiple Bit Upsets. The gathered results pave the way to the integration of reliability and security mechanisms to achieve better results with lower costs.

Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms

“…Specifically, for the case of the PCBC cipher and padding, we can see that we achieve significantly high (≈ 100%) fault detection rates no matter the injected fault multiplicity. We present a comprehensive and more in-depth analysis of this work in [7]. Work is currently being done to extend this work by considering a wider variety of CNNs, while also accounting for the attribute of integrity.…”

Compact Functional Testing for Neuromorphic Computing Circuits

“…Algorithmic-based error detection and correction methods using checksum arithmetic are discussed in [13], [26]- [29]. On-line test methods are proposed in [30] based on Software Test Libraries (STL), in [31] based on a simplified metric of dynamic power consumption, and in [32] based on encrypting weights in the memory with an encryption algorithm that spreads single bitflips extending them to multiple bit-flips and checking if the padding bytes used for the encryption to work properly are correctly decrypted.…”

Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives

“…In the case where the weights of the DNN model are loaded encrypted in the memory, an on-line test scheme is proposed in [165] that employs the padding bits. Padding is used to add a number of bytes to the plaintext to reach a multiple of 16 bytes (i.e., 128 bits) since encryption is performed on 128bit blocks.…”

“…These solutions bring in new challenges for testing. For instance, in-memory solutions may require understanding and creation Physical-aware DFT [136] DFT overhead Function-aware DFT [134], [135], [145] Complete DFT solutions for large heterogeneous systems Functional test generation [127], [146]- [156] Memory-hungry designs On-line test [157]- [165] New market demands (i.e., 0 DPPM for automotive, on-line test)…”