Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs

Abstract

The goal of modern high performance computing platforms is to combine low power consumption and high throughput. Within the European Processor Initiative (EPI), such an SoC platform to meet the novel exascale requirements is built and investigated. As part of this project, we introduce an embedded Field Programmable Gate Array (eFPGA), adding flexibility to accelerate various workloads. In this article, we show our approach to design the eFPGA tile that supports the EPI SoC. While eFPGAs are inherently reconfigurable, their initial design has to be determined for tape-out. The design space of the eFPGA is explored and evaluated with different configurations of two HPC workloads, covering control and dataflow heavy applications. As a result, we present a well-balanced eFPGA design that can host several use cases and potential future ones by allocating 1% of the total EPI SoC area. Finally, our simulation results of the architectures on the eFPGA show great performance improvements over their software counterparts.

Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA

“…Our preliminary results show that we can map four number converters, the control logic and the DMA on an eFPGA with 1.5 mm 2 total area using a 12 nm TSMC process. Therefore, we configured the eFPGA resources to fit the application before hardening, as described in [10]. With our application running at 100 MHz, we can achieve a theoretical trough-put of 400 M word/s, which is sufficient for fast DNN acceleration.…”