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Within the European Processor Initiative (EPI) an objective is build an embedded High-Performance processing platform for future automotive applications such as autonomous driving. An embedded Field-Programmable-Gate-Array (eF-PGA) enables the platform to be extended for future needs and requirements by various stakeholders. In this paper we give an overview about the project and our contributions to define the architecture of the eFPGA, which is suitable for the automotive market. Therefore, we describe our concept to explore the eFPGA architecture. It is motivated by a sound use case that deals with face recognition based on current neural networks. During the scope of the work we describe how the application is carefully mapped on the different domains of the EPI platform to make it more safe and secure as well as performant. As a result, we will find an apt eFPGA configuration, which can host common but also future neural network applications and a mapping of common image processing tasks.

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The goal of modern high performance computing platforms is to combine low power consumption and high throughput. Within the European Processor Initiative (EPI), such an SoC platform to meet the novel exascale requirements is built and investigated. As part of this project, we introduce an embedded Field Programmable Gate Array (eFPGA), adding flexibility to accelerate various workloads. In this article, we show our approach to design the eFPGA tile that supports the EPI SoC. While eFPGAs are inherently reconfigurable, their initial design has to be determined for tape-out. The design space of the eFPGA is explored and evaluated with different configurations of two HPC workloads, covering control and dataflow heavy applications. As a result, we present a well-balanced eFPGA design that can host several use cases and potential future ones by allocating 1% of the total EPI SoC area. Finally, our simulation results of the architectures on the eFPGA show great performance improvements over their software counterparts.

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