Towards scalable I/O on a many-core architecture

Hicks, Michael A.; Tol, M.W. van; Jesshope, Chris

doi:10.1109/icsamos.2010.5642045

Cited by 6 publications

(4 citation statements)

References 10 publications

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“…Virtual memory is implemented using a MMU shared by all cores, so that all threads appear to run in the same logical address space. Some Microgrid cores have a direct asynchronous interface to off-chip I/O which supports multiple in-flight split-phase transactions [31], to maximize bandwidth in streaming applications.…”

Section: Realization and Evaluationmentioning

confidence: 99%

Apple-CORE: Microgrids of SVP Cores -- Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management

Poss

Lankamp

Yang

et al. 2012

2012 15th Euromicro Conference on Digital System Design

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To harness the potential of CMPs for scalable, energy-efficient performance in general-purpose computers, the Apple-CORE project has co-designed a general machine model and concurrency control interface with dedicated hardware support for concurrency management across multiple cores. Its SVP interface combines dataflow synchronisation with imperative programming, towards the efficient use of parallelism in generalpurpose workloads. The corresponding hardware implementation provides logic able to coordinate single-issue, in-order multithreaded RISC cores into computation clusters on chip, called Microgrids. In contrast with the traditional "accelerator" approach, Microgrids are intended to be used as components in distributed systems on chip that consider both clusters of small cores and optional larger cores optimized towards sequential performance as system services shared between applications. The key aspects of the design are asynchrony, i.e. the ability to tolerate operations with irregular long latencies, a scale-invariant programming model, a distributed vision of the chip's structure, and the transparent performance scaling of a single program binary code across multiple cluster sizes. This paper describes the execution model, the core micro-architecture, its realization in a many-core, general-purpose processor chip and its software environment. The reference chip parameters include 128 cores, a 4 MB on-chip distributed cache network and four DDR3-1600 memory channels. This paper presents cycle-accurate simulation results for various key algorithmic and cryptographic kernels. The results show good efficiency in terms of the utilisation of hardware despite the high-latency memory accesses and good scalability across relatively large clusters of cores.

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Section: Realization and Evaluationmentioning

confidence: 99%

Apple-CORE: Microgrids of SVP Cores -- Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management

Poss

Lankamp

Yang

et al. 2012

2012 15th Euromicro Conference on Digital System Design

Self Cite

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“…However, MGSim and Microgrids support relatively large core counts (hundreds), large-scale hardware multithreading for in-core latency tolerance (tenths of hardware threads per core), local scratchpads, a packet-oriented NoC, backward-compatible userspace ISAs (Alpha/SPARC/MIPS), and virtual address translation using a model already similar to our proposal in the previous section: paging requests (TLB faults/refills) caused by compute cores are signalled to a separate core to be handled asynchronously. The core micro-architecture modeled in MGSim is openly documented [23], [24], [25] and its C compiler is GCC-based and open source, which makes the exploration of architectural changes to manycores more tractable.…”

Section: Proof-of-conceptmentioning

confidence: 99%

AM : Towards A Hardware Unix Accelerator for Many-Cores

Poss

Koning

2016

IEEE Trans. Parallel Distrib. Syst.

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This article advocates the use of new architectural features commonly found in many-cores to replace the machine model underlying Unix-like operating systems. We present a general Abstract Many-core Machine Model (AM 3), a proof-of-concept implementation and first evaluation results in the context of an emerging many-core, hardware multi-threaded architecture without support for interrupts. Our proposed approach makes it possible to reuse off-the-shelf multithreaded/multiprocess software on massively parallel architectures, without need to change code to use custom programming models like CUDA or OpenCL. Benefits include higher hardware utilization, higher performance and higher energy efficiency for workloads common to general-purpose platforms, such as in datacenters and Clouds. The benefits also include simpler software control over the hardware platform, an enabling factor for the further evolution of parallel programming languages.

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“…The instruction set of the I/O core supports the I/O infrastructure and are connected to the delegation network of the Microgrid. We do not simulate I/O cores in the current implementation of HLSim, therefore we refer readers to [16,21,31] for the I/O management in the Microgrid.…”

Section: I/o In the Microgridmentioning

confidence: 99%

Microgrid - The microthreaded many-core architecture

Uddin

2013

Preprint

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Traditional processors use the von Neumann execution model, some other processors in the past have used the dataflow execution model. A combination of von Neuman model and dataflow model is also tried in the past and the resultant model is referred as hybrid dataflow execution model. We describe a hybrid dataflow model known as the microthreading. It provides constructs for creation, synchronization and communication between threads in an intermediate language. The microthreading model is an abstract programming and machine model for many-core architecture. A particular instance of this model is named as the microthreaded architecture or the Microgrid. This architecture implements all the concurrency constructs of the microthreading model in the hardware with the management of these constructs in the hardware.

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Towards scalable I/O on a many-core architecture

Cited by 6 publications

References 10 publications

Apple-CORE: Microgrids of SVP Cores -- Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management

Apple-CORE: Microgrids of SVP Cores -- Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management

AM : Towards A Hardware Unix Accelerator for Many-Cores

Microgrid - The microthreaded many-core architecture

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