Towards scalable network emulation: Channel accuracy versus implementation resources

Abstract

Abstract-Channel emulators are valuable tools for controllable and repeatable wireless experimentation. Often, however, the high cost of such emulators preclude their widespread usage, especially in large-scale wireless networks. Moreover, existing channel emulators offer either very realistic channels for simplistic topologies or complex topologies with highly-abstracted, lowfidelity channels. To bridge the gap in offering a low-cost channel emulation solution which can scale to a large network size, in this paper, we study the tradeoff in channel emulation fidelity versus the hardware resources consumed using both analytical modeling and FPGA-based implementation. To reduce the memory footprint of our design, we optimize our channel emulation using an iterative structure to generate the Rayleigh fading channel. In addition, the channel update rate and word length selection are also evaluated in the paper which greatly improve the efficiency of implementation. We then extend our analysis of a single channel to understand how the implementation scales for the emulation of a large-scale wireless network, showing that up to 24 vehicular channels can be emulated in real-time on a single Virtex-4 FPGA.

Wireless Networking Testbed and Emulator (WiNeTestEr)

“…In WiNeTestEr a single FPGA is required to process two different input signals and produce up to 6 outputs (two RF boards) with different channel conditions. We proposed a novel structure to implement SOS based channel generation specifically for this purpose [14]. With this structure, the generation of one Rayleigh channel consumes only 1 unit memory resource ( ∼ RAMB16) of the 376 available in the FPGA.…”

Weibull and Suzuki fading channel generator design to reduce hardware resources

“…Clearly, to ensure accuracy of the emulation, large look-up tables and consequently large memories are required. An alternate iterative approach to generate SOSbased Rayleigh channels is proposed in [14], using an AR model. This iterative generation is given by,…”

“…Based on (11), to generate the I-Q components of the Weibull fading channel, the following 4 main steps are needed: 1) Generate Rayleigh fading channel (r 2 R (n)) using the iterative structure proposed in [14]; 2) Calculate the natural logarithm (ln r 2 R (n)) and the square root (|r R (n)| = r 2 R (n)) of r A pictorial description of the major computational blocks in the proposed Weibull fading channel generation scheme is given in Fig. 2.…”

“…4 is also able to provide the values of ln r 2 R (n) and |r R (n)| simultaneously. After the desired number of iterations of (14), the output on the x branch equals the square root (|r…”

“…Further, the proposed emulation scheme can also be used to generate Lognormal and Suzuki fading channels and the accuracy of such a generation method is illustrated. To further reduce the memory expenditure of the emulation, a novel Rayleigh channel generation scheme proposed in our prior work [14] is also utilized.…”