Towards scalable reliability frameworks for error prone CMPs

Sloan, Joseph; Kumar, Rakesh

doi:10.1145/1629395.1629432

Cited by 8 publications

(5 citation statements)

References 12 publications

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“…Baleani, et al have investigated the trade-offs of lockstep and more loosely coupled redundant execution [1]. Sloan and Kumar have developed a framework which distributes voting logic to support efficient nMR in chip multiprocessors (CMPs) [6]. Subramanyan, et al reduce throughput losses in a CMP when a redundant thread lags the leading thread by forwarding loaded values and branch outcomes [7].…”

Section: Related Workmentioning

confidence: 99%

Reducing the cost of redundant execution in safety-critical systems using relaxed dedication

Meyer

George

Calhoun

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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Abstract-We introduce on-demand redundancy, a set of architectural techniques that leverage the tightly-coupled nature of components in systems-on-chip to reduce the cost of safety-critical systems. On-demand redundancy eases the assumptions that traditionally segregate the execution of critical and non-critical tasks (NCTs), making resources available for critical tasks at potentially arbitrary points in both space and time, and otherwise freeing resources to execute non-critical tasks when critical tasks are not executing. Relaxed dedication is one such technique that allows non-critical tasks to execute on critical task resources. Our results demonstrate that for a wide variety of applications and architectures, relaxed dedication is more cost-effective than a traditional approach that employs dedicated resources executing in lockstep. Applied to dual-modular redundancy (DMR), relaxed dedication exposes 73% more NCT cycles than traditional DMR on average, across a wide variety of usage scenarios.

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Section: Related Workmentioning

confidence: 99%

Reducing the cost of redundant execution in safety-critical systems using relaxed dedication

Meyer

George

Calhoun

et al. 2011

2011 Design, Automation &Amp; Test in Europe

View full text Add to dashboard Cite

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“…Subramanyan, et al reduce throughput losses in a multiprocessor when a redundant thread lags the leading thread by forwarding loaded values and branch outcomes [6]. Sloan and Kumar developed a framework that distributes voting logic to support efficient, dynamic nMR group formation in chip multiprocessors (CMPs) [15].…”

Section: Related Workmentioning

confidence: 99%

Trade-offs in execution signature compression for reliable processor systems

Caplan

Mera

Milder

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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As semiconductor processes scale, making transistors more vulnerable to transient upset, a wide variety of microarchitectural and system-level strategies are emerging to perform efficient error detection and correction computer systems. While these approaches often target various application domains and address error detection and correction at different granularities and with different overheads, an emerging trend is the use of state compression, e.g., cyclic redundancy check (CRC), to reduce the cost of redundancy checking. Prior work in the literature has shown that Fletcher's checksum (FC), while less effective where error detection probability is concerned, is less computationally complex when implemented in software than the more-effective CRC. In this paper, we reexamine the suitability of CRC and FC as compression algorithms when implemented in hardware for embedded safety-critical systems. We have developed and evaluated parameterizable implementations of CRC and FC in FPGA, and we observe that what was true for software implementations does not hold in hardware: CRC is more efficient than FC across a wide variety of target input bandwidths and compression strengths.

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“…DCC [9] presents dynamic coupling DMR by shared bus, it degrades half as fast as mechanisms that rely on static DMR pairs. Joseph [15] dynamically constructs NMR groups though adding vote table in router. SmartCore [16] is a many-core system with redundant cores and multifunction routers including three functions: copying packets, changing the destinations of packets, and rendezvousing and comparing two packets from different nodes.…”

Section: Background and Related Workmentioning

confidence: 99%

“…For low performance overhead if the application requires low reliability, design concept of DVR is not to optimize system for fault-tolerant but to avoid modification to existing highly- Works on-demand dynamically idle redundancy coupling exploiting DVR(this paper) yes yes yes Relax [5] yes no no DCC [9],Joseph [15], no yes no smart-core [16] warped-DMR [19] no no yes optimized micro-architectures. It employs selectively redundancy scope for the different reliability requirements among vary applications.…”

Section: Background and Related Workmentioning

confidence: 99%

Device View Redundancy: An Adaptive Low-Overhead Fault Tolerance Mechanism for Many-Core System

Jia

Zhang

2013

2013 IEEE 10th International Conference on High Performance Computing and Communications &Amp; 2013 IEEE International Conferen

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Continued increasing of fault rate in integrate circuit makes processors more susceptible to errors, especially many-core processor. Meanwhile, most systems or applications do not need full fault coverage, which has excessive overhead. So on-demand fault tolerance is desired for these applications. In this paper, we propose an adaptive low-overhead fault tolerance mechanism for many-core system, called Device View Redundancy (DVR). It treats fault tolerance as a device that can be configured and used by application when high reliability is needed. Nevertheless, DVR exploits the idle resources for lowoverhead fault tolerance, which is based on the observation that the utilization of many-core system is low due to lack of parallelism in application. Finally, the experiment shows that the performance overhead of DVR is reduced by 16%to 98% compared with full Dual Modular Redundancy (DMR).

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Towards scalable reliability frameworks for error prone CMPs

Cited by 8 publications

References 12 publications

Reducing the cost of redundant execution in safety-critical systems using relaxed dedication

Reducing the cost of redundant execution in safety-critical systems using relaxed dedication

Trade-offs in execution signature compression for reliable processor systems

Device View Redundancy: An Adaptive Low-Overhead Fault Tolerance Mechanism for Many-Core System

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