Towards simple, high-performance schedulers for high-aggregate bandwidth switches

Giaccone, Paolo; Prabhakar, Balaji; Shah, Devavrat

doi:10.1109/infcom.2002.1019366

Cited by 74 publications

(62 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The complexity of this algorithm adopted to module-level matching is reduced to N 1.5 , and is still high for large-scale switches. The APSARA algorithm [17] tries to speed up the scheduling process by searching in parallel for the highest weight from reduced space matchings. For example, by swapping any two connections from the matching used in the previous time slot, the APSARA algorithm can find a new matching.…”

Section: Packet Dispatching Scheme For the Mcnsmentioning

confidence: 99%

Packet dispatching using module matching in the modified MSM Clos-network switch

Kleban

2017

Telecommun Syst

View full text Add to dashboard Cite

A modified memory-space-memory (MSM) Closnetwork switch, called MCNS, with a module-level matching packet dispatching scheme, is presented in the paper. The MCNS is a modification of the MSM Clos-network switch proposed to simplify the packet dispatching scheme. In this paper, we evaluate the combinatorial properties of the MCNS, as well as a new module-level matching packet dispatching algorithm. We also show how this algorithm can be implemented in an field-programmable gate array chip. Selected simulation results obtained for the MCNS are compared with the results obtained for the MSM Clos-network switch using other module-level matching algorithms.

show abstract

Section: Packet Dispatching Scheme For the Mcnsmentioning

confidence: 99%

Packet dispatching using module matching in the modified MSM Clos-network switch

Kleban

2017

Telecommun Syst

View full text Add to dashboard Cite

show abstract

“…From both (10) and (11) Consider the policy D and fix θ 0 = 3/2. We know, from Lemma 1, that D is F -work-conserving (in this case, γ = 0 and θ = θ 0 ).…”

Section: Property 2 It Can Never Happen That It Exists J Such Thatmentioning

confidence: 99%

“…But they do not guarantee delay bounds for each packet. Many practical scheduling algorithms [9,10] have been proposed to approximate MWM performance. Their simplicity usually leads to some performance penalties, usually in the form of throughput degradation and/or larger delays.…”

Section: Introductionmentioning

confidence: 99%

Delay bounds for combined input–output switches with low speedup

Giaccone

Leonardi

Prabhakar

et al. 2004

Performance Evaluation

View full text Add to dashboard Cite

“…But the delay performance is unacceptably high. Several algorithms were proposed by Giaccone et al [1] to improve the delay performance. SERENA, which also considers new arrivals, besides using memory, has a much better delay performance than the one in [7].…”

Section: Introductionmentioning

confidence: 99%

An O(1) scheduling algorithm for variable-size packet switching systems

Ye¹,

Shen

Panwar³

2010

2010 48th Annual Allerton Conference on Communication, Control, and Computing (Allerton)

View full text Add to dashboard Cite

Abstract-Internet traffic has increased at a very fast pace in recent years. The traffic demand requires that future packet switching systems should be able to switch packets in a very short time, i.e., just a few nanoseconds. Algorithms with lower computation complexity are more desirable for this high-speed switching design. Among the existing algorithms that can achieve 100% throughut for input-queued switches for any admissible Bernoulli traffic, ALGO3 [1] and EMHW [2] have the lowest computation complexity, which is O(logN ), where N is the number of ports in the switch.In this paper, we propose a randomized scheduling algorithm, which can also stabilize the system for any admissible traffic that satisfies the strong law of large number. The algorithm has a complexity of O(1). Since the complexity does not increase with the size of a switch, the algorithm is highly scalable and a good choice for future high-speed switch designs. We also show that the algorithm can be implemented in a distributed way by using a low-rate control channel. Simulation results show that the algorithm can provide a good delay performance as compared to algorithms with higher computation complexity.

show abstract

Towards simple, high-performance schedulers for high-aggregate bandwidth switches

Cited by 74 publications

References 27 publications

Packet dispatching using module matching in the modified MSM Clos-network switch

Packet dispatching using module matching in the modified MSM Clos-network switch

Delay bounds for combined input–output switches with low speedup

An O(1) scheduling algorithm for variable-size packet switching systems

Contact Info

Product

Resources

About