Towards SRAM leakage power minimization by aggressive standby voltage scaling — Experiments on 40nm test chips

Fan, Xin; Stuijt, Jan; Gemmeke, Tobias

doi:10.1109/dft.2017.8244431

Cited by 2 publications

(1 citation statement)

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“…It can be argued that the overhead of a full FECC is too large, since failed cells can be detected at test time. Alternatively, an extra (fused) bitcolumn or a few spare words could be added [5]. However, an extra bit-column and a single spare word can only mitigate a single error, severely limiting the correction capability and the voltage scaling.…”

Section: A Lower Retention Voltagementioning

confidence: 99%

A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage

Vanhoof,

Dehaene

2024

IEEE Trans. Circuits Syst. I

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In biomedical sensor platforms, low energy consumption is of utmost importance to extend battery life. A dominant contributor in the energy budget of such platforms is the always-on recording memory. Hence, a low energy memory is required. This paper implements such a memory with aggressive voltage scaling to run the memory in the sub-threshold region during retention. Fine grained forward error correction is a key enabler for this. It allows operation of the memory beyond the point of first failure and acts similar to EDAC techniques for timing failure detection in voltage-scaled microcontrollers. The memory is embedded in a RISC-V microcontroller and fabricated in a 22nm FDSOI technology. Measurements show an always-on retention voltage down to 170mV, which results in a total average power of only 5.11uW, a 70% reduction compared to the signoff point. The memory is extensively tested with memtest and found to be fully functional up to 1.2 MHz.

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Section: A Lower Retention Voltagementioning

confidence: 99%