TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network

Vansteenkiste, Elias; Farisi, Brahim Al; Bruneel, Karel; Stroobandt, Dirk

doi:10.1109/tcad.2013.2291659

Cited by 25 publications

(14 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The minimum channel width (CW) of the experiments presented in [2] [11] show an increase in the minimum channel width when using TCONs. However, our results show that the minimum routing channel width of both implementations are the same.…”

Section: Resultsmentioning

confidence: 97%

“…The synthesized PE was subjected to a Place and Route (PaR) tool using the TPaR CAD tool [11]. The PaR was performed using the 4LUT sanitized FPGA architecture from the VPR [15].…”

Section: Resultsmentioning

confidence: 99%

“…Further, with the help of TPLACE and TROUTE, these connections can be placed and routed on to the lower-level physical routing switches thereby reducing the PE intra-connect overhead on the physical LUTs of the FPGA. With the help of TCONs, a significant reduction in routing resource consumption (at least by 40%) has been observed in the experiments of [11]. We aim at similar improvements by using the TCON concept on a VCGRA implementation of a retinal vessel segmentation application.…”

Section: Fully Parameterized Vcgramentioning

confidence: 92%

See 2 more Smart Citations

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

Kulkarni

Vasteenkiste

Stroobandt

et al. 2016

2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

Self Cite

View full text Add to dashboard Cite

Abstract-Field Programmable Gate Arrays (FPGAs) have proven their potential in accelerating High Performance Computing (HPC) Applications. Conventionally such accelerators predominantly use, FPGAs that contain fine-grained elements such as LookUp Tables (LUTs), Switch Blocks (SB) and Connection Blocks (CB) as basic programmable logic blocks. However, the conventional implementation suffers from high reconfiguration and development costs. In order to solve this problem, programmable logic components are defined at a virtual higher abstraction level. These components are called Processing Elements (PEs) and the group of PEs along with the inter-connection network form an architecture called a Virtual Coarse-Grained Reconfigurable Array (VCGRA). The abstraction helps to reconfigure the PEs faster at the intermediate level than at the lower-level of an FPGA.Conventional VCGRA implementations (built on top of the lower levels of the FPGA) use functional resources such as LUTs to establish required connections (intra-connect) within a PE. In this paper, we propose to use the parameterized reconfiguration technique to implement the intra-connections of each PE with the aim to reduce the FPGA resource utilization (LUTs). The technique is used to parameterize the intra-connections with parameters that only change their value infrequently (whenever a new VCGRA function has to be reconfigured) and that are implemented as constants. Since the design is optimized for these constants at every moment in time, this reduces the resource utilization. Further, interconnections (network between the multiple PEs) of the VCGRA grid can also be parameterized so that both the inter-and intraconnect network of the VCGRA grid can be mapped onto the physical switch blocks of the FPGA. For every change in parameter values a specialized bitstream is generated on the fly and the FPGA is reconfigured using the parameterized run-time reconfiguration technique. Our results show a drastic reduction in FPGA LUT resource utilization in the PE by at least 30% and in the intra-network of the PE by 31% when implementing an HPC application.

show abstract

Section: Resultsmentioning

confidence: 97%

“…The synthesized PE was subjected to a Place and Route (PaR) tool using the TPaR CAD tool [11]. The PaR was performed using the 4LUT sanitized FPGA architecture from the VPR [15].…”

Section: Resultsmentioning

confidence: 99%

Section: Fully Parameterized Vcgramentioning

confidence: 92%

See 1 more Smart Citation

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

Kulkarni

Vasteenkiste

Stroobandt

et al. 2016

2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

Self Cite

View full text Add to dashboard Cite

show abstract

“…This technique can be applied in hardware systems that can be parameterized with parameters that define different circuit instances that can be optimized on the fly by reconfiguring for the current set of parameter values. Lately this tool has been extended and can also support parameterisation of both logic and routing resources [7]. This technique is visualised in Figure 2.…”

Section: A Parameterised Fpga Configurationsmentioning

confidence: 99%

Efficient Hardware Debugging Using Parameterized FPGA Reconfiguration

Kourfali

Stroobandt

2016

2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

Self Cite

View full text Add to dashboard Cite

Abstract-Functional errors and bugs inadvertently introduced at the RTL stage of the design process are responsible for the largest fraction of silicon IC re-spins. Thus, comprehensive functional verification is the key to reduce development costs and to deliver a product in time. The increasing demands for verification led to an increase in FPGA-based tools that perform emulation. These tools can run at much higher operating frequencies and achieve higher coverage than simulation. However, an important pitfall of the FPGA tools is that they suffer from limited internal signal observability, as only a small and preselected set of signals is guided towards (embedded) trace buffers and observed. This paper proposes a dynamically reconfigurable network of multiplexers that significantly enhance the visibility of internal signals. It allows the designer to dynamically change the small set of internal signals to be observed, virtually enlarging the set of observed signals significantly. These multiplexers occupy minimal space, as they are implemented by the FPGA's routing infrastructure.

show abstract

“…An overview of this tool flow is given in Section 3. The new placement and routing step is presented in Vansteenkiste et al [2014]. In this work, we focus on the technology mapping step of the new FPGA tool flow.…”

Section: Introductionmentioning

confidence: 99%

Tconmap

Heyse

Farisi

Bruneel

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

Self Cite

View full text Add to dashboard Cite

Parameterised configurations are FPGA configuration bitstreams in which the bits are defined as functions of user-defined parameters. From a parameterised configuration, it is possible to quickly and efficiently derive specialised, regular configuration bitstreams by evaluating these functions. The specialised bitstreams have different properties and functionality depending on the chosen values of the parameters. The most important application of parameterised configurations is the generation of specialised configuration bitstreams for Dynamic Circuit Specialisation, a technique for optimising circuits at runtime using partial reconfiguration of the FPGA.Generating and using parameterised configurations requires a new FPGA tool flow. In this article, we present a new technology mapping algorithm for parameterised designs, called TCONMAP, that can be used to produce parameterised configurations in which both the configuration of the logic blocks and routing is a function of the parameters. In our experiments, we demonstrate that in using TCONMAP, the depth and area of the mapped circuit is close to the minimal depth and area attainable. Both Dynamic Circuit Specialisation and fine-grained modular reconfiguration are extracted by TCONMAP from the HDL description of the design requiring only simple parameter annotations.

show abstract

TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network

Cited by 25 publications

References 17 publications

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

Efficient Hardware Debugging Using Parameterized FPGA Reconfiguration

Tconmap

Contact Info

Product

Resources

About