2022
DOI: 10.1109/tcsi.2022.3200410
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Trade-Off-Oriented Impedance Optimization of Chiplet-Based 2.5-D Integrated Circuits With a Hybrid MDP Algorithm for Noise Elimination

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Cited by 5 publications
(1 citation statement)
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“…Owing to growing concerns about traditional planar integrated circuits (ICs) suffering from a bottleneck of integrating the every-increasing transistors with a single package, the 3-D system integration with chiplets has emerged as a promising solution to embody the intrinsic value of "More-than-Moore" by dividing a monolithic system-on-chip (SoC) into several functional blocks and then interconnecting them, thus achieving highly heterogeneous integrations [1], [2]. An important strategy greatly contributing to the promotion of 3-D system integration with chiplets is the through-silicon via (TSV), which vertically interconnects the stacked dies, and naturally paves a path to the next-generation heterogeneity [3], [4].…”
Section: Introductionmentioning
confidence: 99%
“…Owing to growing concerns about traditional planar integrated circuits (ICs) suffering from a bottleneck of integrating the every-increasing transistors with a single package, the 3-D system integration with chiplets has emerged as a promising solution to embody the intrinsic value of "More-than-Moore" by dividing a monolithic system-on-chip (SoC) into several functional blocks and then interconnecting them, thus achieving highly heterogeneous integrations [1], [2]. An important strategy greatly contributing to the promotion of 3-D system integration with chiplets is the through-silicon via (TSV), which vertically interconnects the stacked dies, and naturally paves a path to the next-generation heterogeneity [3], [4].…”
Section: Introductionmentioning
confidence: 99%