Tradeoff between short channel effect and mobility in strained-Si nMOSFETs

Abstract

A strained-Si CMOS technology with improved immunity to short channel effects (SCE) and reduced defect density was demonstrated at a gate length of 80 nm. The driving current was enhanced by 25% using 20% Ge content relaxed SiGe buffer. The trade-offs between electron mobility enhancement and SCE control for different Si-cap layer thicknesses and various Ge contents in the relaxed-SiGe virtual substrate are investigated. Besides, our work presents the optimum processes window for strained-Si devices in advanced CMOS technology.

Evaluation of Interface Property and DC Characteristics Enhancement in Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Using Stress Memorization Technique

“…The introduction of tensile-strained Si on fully relaxed SiGe virtual substrates for n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) can enhance electron mobility. [2][3][4][5] However, a drawback of these substrates is that SiGe virtual substrate usually accompanies the roughness of SiO 2 /Si interface inheriting from the SiGe graded buffer layer. On the other hand, the use of process-induced stressor engineering has been intensively studied.…”