Tradeoffs between settling time and jitter in phase locked loops

Paliwal, Pallavi; Laad, Priyank; Sattineni, Mohanrao; Gupta, Shalabh

doi:10.1109/mwscas.2013.6674757

Cited by 12 publications

(5 citation statements)

References 10 publications

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“…where C mix + is the total node capacitance at the drain of mixer switching transistor. Equation (7) shows spur-generation at 2f f rac offset from the DTC frequency. This spur occurs due to phase-mismatches (ǫ) in the oscillator input (LO), leading to incomplete rejection of the image-component signal.…”

Section: Dual-phase Dds Based Dtc Implementationmentioning

confidence: 99%

“…Equation ( 6)- (7) highlight that interconnect matching is crucial to avoid in-band spur-generation at the DTC output. Apart from the interconnect and device mismatches, the transconductance non-linearities of the mixer-switches results in generation of spurious tones at 4f f rac offset with respect to the output frequency.…”

Section: Dual-phase Dds Based Dtc Implementationmentioning

confidence: 99%

“…3. We have shown a lock-time enhanced DPLL architecture incorporating DDS based DTC in [6], which uses a switched loop with variable phase-detection and proportional-integralderivative (PID) controller based finite state machine (FSM) [7] to achieve a record low settling time. For attaining low jitter, most of the DDS based DTCs incorporate harmonic-rejection, polyphase mixing and/or antialiasing filtering [9], which result in high power dissipation.…”

Section: Introductionmentioning

confidence: 99%

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A Phase Lookahead DTC for Fast Settling Switched Loop DPLL

Paliwal,

Yadav,

Gupta

2018

Preprint

Self Cite

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In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency translation range. To achieve this performance, we present a dualphase direct digital synthesizer (DDS) based DTC with phaselookahead mechanism. The proposed technique of variable phaseadvancement enhances the frequency translation range, without excessive power consumption. A 5-GHz digital phase locked loop (DPLL) with switched loop, incorporating this DDS based DTC, is implemented in CMOS65 nm-LL technology. The proposed DDS based DTC is able to perform fractional shift upto ±80 MHz with 100 MHz reference clock, using 3 mW of power from 1.2 V supply. A simple look-up table based foreground-calibration of phase-to-amplitude converter (PAC) in DDS improves the peak INL of the DTC to 0.25 ps. Hence, with the proposed DTC and a proportional-integral-derivative (PID) controller based loop, we are able to achieve a low-jitter fractional-N DPLL with fastest settling time of 1-µs reported until now for fractional-N PLLs.

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Section: Dual-phase Dds Based Dtc Implementationmentioning

confidence: 99%

Section: Dual-phase Dds Based Dtc Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Phase Lookahead DTC for Fast Settling Switched Loop DPLL

Paliwal,

Yadav,

Gupta

2018

Preprint

Self Cite

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“…But a TDC with high resolution and wide-linear range is area consuming and power hungry. Compared with the TDC based ADPLL, the bang-bang phase/frequency detector (BBPFD) based ADPLLs (BBPLLs) which use only 1-bit phase-detecting output have advantages of simplicity, low power and low area [8][9][10][11][12][13][14][15][16][17] .…”

Section: Introductionmentioning

confidence: 99%

“…Consequently, traditional BBPLLs are still unsuitable for the frequency hopping systems and fast recovering applications, which require a short locked time of the PLL. Several techniques have been proposed to reduce the locked time of the BBPLL [13][14][15][16][17] . These techniques are based on the idea of coarse frequency searching or dynamically calibrating loop band-width, according to the detecting phase error.…”

Section: Introductionmentioning

confidence: 99%

A fast-locking bang-bang phase-locked loop with adaptive loop gain controller

Yang

Zhang

et al. 2018

J. Semicond.

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This paper proposes a fast-locking bang-bang phase-locked loop (BBPLL). A novel adaptive loop gain controller (ALGC) is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector (BBPFD) with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm2. Measured results show that the BBPLL operates at a frequency range from 0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1 μs @ 100 MHz frequency jump. The figure-of-merit of the fast-locking BBPLL is −334 dB.

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A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting

Cheong

Kim²

2021

IEEE Access

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This presents an all-digital phase-locked loop (ADPLL) system using triple-stage phaseshifting (TSPS) for fast locking. At the first stage, a phase-pulling multiplexer linearly pulls the phase of a feedback signal until the phase offset between the feedback and reference signals becomes sufficiently small. Then, a toggling phase-shifting in the second stage achieves further reduction of the phase offset by delaying the feedback and reference signals. A subsequent adaptive target index-shifting stage then detects fine-locking in frequency and rapidly performs phase-locking to the present phase of the feedback signal instead of the initial target phase. This TSPS-ADPLL avoids frequency peaking by choosing oscillator control codes that generate frequencies below or near the target. Fabricated in a 28nm CMOS process, this ADPLL can lock within 1.0s, producing a 2.4GHz output clock without frequency peaking. It has an RMS jitter of 2.53ps and draws 2.89mW from a 1.0V supply.INDEX TERMS Fast-locking, phase-shifting, frequency peaking, frequency search, digital clock generator, all-digital phase-locked loop (ADPLL).

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Tradeoffs between settling time and jitter in phase locked loops

Cited by 12 publications

References 10 publications

A Phase Lookahead DTC for Fast Settling Switched Loop DPLL

A Phase Lookahead DTC for Fast Settling Switched Loop DPLL

A fast-locking bang-bang phase-locked loop with adaptive loop gain controller

A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting

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