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In most PLL architectures, trade-off exists between settling time and jitter performance, which is ignored during Figure of Merit calculation. This work derives a new Figure of Merit for PLL, which has settling time as added performance parameter, along with jitter and power. Here, the trade-off between settling time and jitter is analyzed theoretically, and with behavioral simulations for (i) linear Time-to-Digital based PLL (ii) non-linear Bang-Bang Phase Detector based PLL (iii) Hybrid PLL with adaptive gain, to obtain settling time vs. jitter relation, based on which commonly used Figure of Merit is modified. To understand trade-off relation between settling time and jitter for Bang-Bang Phase Detector based PLL, this work also derives settling time equation for non-linear PLL, by using recursive time-domain equations.

With every new technology node, scaling down of Device-to-Interconnect Capacitance ratio causes Interconnect delay to become bottleneck for circuit perfomance. To mitigate this effect, interconnect routing area on-chip should be minimized for improved power-delay product. In this aspect, FinFET with multiple fins per lithographic pitch gains more advantage, in comparison to Planar Device; since, such FinFET devices allow increase of electrical width without increasing device layout area and thus, interconnect capacitance is comparatively lower. Therefore, minimum delay could be achieved for lesser device width, and thus, with lower power. This paper proves the perfomance enhancement with such FinFET Device for Mux Circuit; and aims to find out Optimum Design Space for Mux Circuit, at 22nm technology node, with practical value of Interconnect Capacitive load (extrapolated from circuit layout in current technology node).

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