2009 IEEE 8th International Conference on ASIC 2009
DOI: 10.1109/asicon.2009.5351599
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Transaction level model of NoC based on SystemC

Abstract: This paper presents a transaction-level on-chip communication network model, including routers and links, which can be easily employed in a system-level system-onchip simulation framework for early functional verification and architecture analysis. The model is capable ofproviding NoC's latency and throughput information during simulating process and developed in SystemC to achieve high simulation speed'.

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