Transaction Security System

Abraham, Denis; Dolan, G. M.; Double, G. P.; Stevens, Jennie

doi:10.1147/sj.302.0206

Cited by 115 publications

(52 citation statements)

References 5 publications

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“…A protection measure is adequate if the assumed effort to break it supersedes the expected benefits of the attack scenario. The classic taxonomy [11] for hardware security distinguishes between low class, middle class, and high class attacker profiles. In reality, a more fine-grained classification might be necessary.…”

Section: B Fpga Design Security Issuesmentioning

confidence: 99%

A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs

Maes

Schellekens

Verbauwhede

2012

IEEE Trans.Inform.Forensic Secur.

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Abstract-Currently achievable intellectual property (IP) protection solutions for field-programmable gate arrays (FPGAs) are limited to single large "monolithic" configurations. However, the ever growing capabilities of FPGAs and the consequential increasing complexity of their designs ask for a modular development model, where individual IP cores from multiple parties are integrated into a larger system. To enable such a model, the availability of IP protection at the modular level is imperative. In this work, we propose an IP protection mechanism for FPGA designs at the level of individual IP cores, by making use of the self-reconfiguring capabilities of modern FPGAs and deploying a trusted third party to run a metering service, similar to the work of Güneysu et al. and Drimer et al. The proposed scheme makes it possible to enforce a pay-per-use licensing scheme which holds considerable advantages, both for IP core providers as well as for system integrators. Moreover, the scheme has a minimal implementation overhead and is the first of its kind to be solely based on primitives that are already available in recent commercially available FPGA devices. This allows for an immediate and feasible deployment, in contrast to earlier proposed solutions.Index Terms-Cloning, design security, field-programmable gate array (FPGA), hardware metering, intellectual property (IP) protection, reverse-engineering, soft intellectual property (IP).

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Section: B Fpga Design Security Issuesmentioning

confidence: 99%

A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs

Maes

Schellekens

Verbauwhede

2012

IEEE Trans.Inform.Forensic Secur.

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“…Для идентифицированных активов используется перечень угроз и их классифи-кация с учетом известных типовых разновидностей угроз [3]. Далее классифициру-емые угрозы сопоставляются с минимальным уровнем нарушителя, необходимым для реализации угрозы в соответствии с моделью Арбахама [6], [7]. На основе этого определяется вероятность возникновения угрозы, выраженная оценкой: низкая , средняя или высокая .…”

Section: реализация и оценка фрагмента защищенной системы умного домаunclassified

Design and Security Analysis of a Fragment of Internet of Things Telecommunication System

Alexandrov

Desnitsky

Chaly

2016

Model. anal. inf. sist.

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“…For exemple, the under voltage technique [2] or the combination of the cipher instruction search attack realised by M. Khun and described in [2] which consists in recognizing enciphered instructions from their effect and the use of a focused ion beam workstation to access the EEP-ROM. A taxonomy of attackers has been done in [1], to realise the fault attack describe above, we consider that we were a class II attacker (knowledge insider). In order to perform the scan, under voltage and cipher instruction search, the attacker must be a class III, i.e.…”

Section: Tate and Ate Pairingsmentioning

confidence: 99%

What about Vulnerability to a Fault Attack of the Miller’s Algorithm During an Identity Based Protocol?

Mrabet

2009

Advances in Information Security and Assurance

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Abstract.We complete the study of [16] and [20] about the Miller's algorithm. The Miller's algorithm is a central step to compute the Weil, Tate and Ate pairings. The aim of this article is to analyse the weakness of the Miller's algorithm when it undergoes a fault attack. We prove that the Miller's algorithm is vulnerable to a fault attack which is valid in all coordinate systems, through the resolution of a nonlinear system. We show that the final exponentiation is no longer a counter measure to this attack for the Tate and Ate pairings.

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Transaction Security System

Cited by 115 publications

References 5 publications

A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs

A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs

Design and Security Analysis of a Fragment of Internet of Things Telecommunication System

What about Vulnerability to a Fault Attack of the Miller’s Algorithm During an Identity Based Protocol?

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