Transactional Memory, 2nd edition

Harris, Tim; Larus, James R.; Rajwar, Ravi

doi:10.2200/s00272ed1v01y201006cac011

Cited by 237 publications

(240 citation statements)

References 246 publications

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“…We do not argue against such so-called relaxed memory models (and certainly not against code optimizations) if they 'ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results' [34,Abstract]. However we insist that IF the effects of such techniques are behaviorally relevant for the problem the programmer is asked to solve, THEN this should be described by a precise model through which the programmer can understand, check and justify that his code does what it is supposed to do.…”

Section: Sequential Consistency Versus Relaxed Memory Modelsmentioning

confidence: 97%

Concurrent abstract state machines

Börger

Schewe

2015

Acta Informatica

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A concurrent Abstract State Machine (ASM) is a family of agents each equipped with a sequential ASM to execute. We define the semantics of concurrent ASMs by concurrent ASM runs which overcome the problems of Gurevich's distributed ASM runs and generalize Lamport's sequentially consistent runs. A postulate characterizing an intuitive understanding of concurrency is formulated. It allows us to state and prove an extension of the sequential ASM thesis to a concurrent ASM thesis.

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Section: Sequential Consistency Versus Relaxed Memory Modelsmentioning

confidence: 97%

Concurrent abstract state machines

Börger

Schewe

2015

Acta Informatica

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“…Transactional Memory (TM): TM [9] is a promising technique that helps with parallel program development by abstracting away the complexity of managing shared data. TM uses optimistic concurrency, assuming that conflicting data accesses will not occur; in case a conflict occurs then one or more transactions must abort, undoing all tentative data updates.…”

Section: Use Casesmentioning

confidence: 99%

“…To benefit from the additional performance offered by these multi-core chips, various novel architecture implementations have been proposed, such as speculative multithreading [10], lock elision [13], or hardware transactional memory [9]. All of these proposals Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Section: Introductionmentioning

confidence: 99%

Circuit design of a dual-versioning L1 data cache for optimistic concurrency

Seyedi

Armejach

Cristal

et al. 2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this new cache architecture, each dvSRAM cell has two cells, a main cell and a secondary cell, which keep two versions of the same data. These values can be accessed, modified, moved back and forth between the main and secondary cells within the access time of the cache. We design and simulate a 32-KB dual-versioning L1 data cache with 45-nm CMOS technology at 2GHz processor frequency and 1V supply voltage, which we describe in detail. We also introduce three well-known use cases that make use of optimistic concurrency execution and that can benefit from our proposed design. Moreover, we evaluate one of the use cases to show the impact of the dual-versioning cell in both performance and energy consumption. Our experiments show that large speedups can be achieved with acceptable overall energy dissipation.

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“…threads will run parallel and improve system performance, but the effect of their execution will appear linear. Unlike database transactions, transactional memory instructions are meant to be short span transactions that access a relatively smaller number of memory locations [1]. Transactional Memory systems can be purely hardware based (Hardware based Transactional Memory or HTM) [2], software-only (Software Transactional Memory or STM) [3] or hybrid.…”

Section: Introductionmentioning

confidence: 99%

A New Contention Management Technique for Obstruction Free Transactional Memory

Ghosh

Sahin

Silsarma

et al. 2014

Computer Information Systems and Industrial Management

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Part 2: AlgorithmsInternational audienceTransactional Memory, one of the most viable alternatives to lock based concurrent systems, was explored by the researchers for practically implementing parallel processing. The goal was that threads will run parallel and improve system performance, but the effect of their execution will be linear. In STM, the non-blocking synchronization can be implemented by Wait-Freedom, Lock-Freedom or Obstruction-Freedom philosophy. Though Obstruction Free Transactional Memory (OFTM) provides the weakest progress guarantee, this paper concentrates upon OFTM because of its design flexibility and algorithmic simplifications. In this paper, the major challenges faced by two state of the art OFTMs viz. Dynamic Software Transactional Memory (DSTM) and Adaptive Software Transactional Memory (ASTM), have been addressed and an alternative arbitration strategy has been proposed that reduces the abort percentage both in case of Read-Write as well as Write-Write conflicts

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Transactional Memory, 2nd edition

Cited by 237 publications

References 246 publications

Concurrent abstract state machines

Concurrent abstract state machines

Circuit design of a dual-versioning L1 data cache for optimistic concurrency

A New Contention Management Technique for Obstruction Free Transactional Memory

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