Transfer printing of CVD graphene FETs on patterned substrates

Abstract

We describe a simple and scalable method for the transfer of CVD graphene for the fabrication of field effect transistors. This is a dry process that uses a modified RCAcleaning step to improve the surface quality. In contrast to conventional fabrication routes where lithographic steps are performed after the transfer, here graphene is transferred to a pre-patterned substrate. The resulting FET devices display nearly zero Dirac voltage, and the contact resistance between the graphene and metal contacts is on the order of 910 ± 340 Ω µm. This approach enables formation of conducting graphene channel lengths up to one millimeter. The resist-free transfer process provides a clean graphene surface that is promising for use in high sensitivity graphene FET biosensors.

van der Waals Contact Engineering of Graphene Field-Effect Transistors for Large-Area Flexible Electronics

“…(see Figure S6, S7). While this aspect has not been highlighted in previous studies, 18,21 such detail is critical for realizing a high-performance bottom contact. Given the recently developed large-area, high quality and low-cost graphene synthesis and transfer technique, 38,39 this method can be potentially extended for large-area, cost-effective GFET fabrication.…”

“…In fact, this premise has only been tested by a small number of preliminary bottom-contact studies, with the state-of-the-art GFET with vdW graphene-metal interaction showing a contact resistance of approximately1000 Ω·µm. 18,21 Here, by engineering the graphene-metal vdW contact with various 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 4 contact geometries, it is possible to significantly improve the contact quality, resulting in an ultralow contact resistance (down to 65 Ω·µm and most of values under 200 Ω·µm). This result is rather competitive with the values from the state-of-the-art top-and edge-contact devices (see Table S1).…”

“…For instance, in Ref 23 , when a bottom contact electrode with an effective height of ~2 nm was employed (the electrodes were deposited in a pre-etched trench), only a minor improvement in carrier injection was observed. By contrast, in Ref 18 , a much increased contact height of 100 nm was used, but the contact length was fixed at 10 µm and the effect of varying this latter parameter was not investigated. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 11,12,15,26,36 blue squares, data from refs; 14,16 red triangles, data from refs; 6,7,9,10,28,37 red circles, data from ref; 27 green circles, data from refs; 8,18,23 earthy yellow diamond, data from ref.…”

“…By contrast, in Ref 18 , a much increased contact height of 100 nm was used, but the contact length was fixed at 10 µm and the effect of varying this latter parameter was not investigated. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 11,12,15,26,36 blue squares, data from refs; 14,16 red triangles, data from refs; 6,7,9,10,28,37 red circles, data from ref; 27 green circles, data from refs; 8,18,23 earthy yellow diamond, data from ref. 26 In this work, we systematically explored the influence of the contact geometry in a bottom contact device by adjusting the contact height and length (denoted as ConH and ConL, referring to the height and the length of the contact electrodes) between 1.8 nm-80 nm and 10 µm-30 µm, respectively.…”

Can Graphene Bilayers Be the Membrane Mimetic Materials? Ion Channels in Graphene-Based Nanostructures

“…Another different mechanism of the membrane self-assembly, and hence, the membrane channel assembly, occurs under the templating conditions, which is simulated by the formation of the graphene films on various catalytic and ultramicrostructured surfaces (e.g. for obtaining FET and other ion-selective structures [139,140]).…”