Transform Competition for Temporal Prediction in Video Coding

Kim

IEEE Trans. Circuits Syst. Video Technol.

et al. 2021

In the past decade, the development of transform coding techniques has achieved significant progress and several advanced transform tools have been adopted in the new generation Versatile Video Coding (VVC) standard. In this paper, a brief history of transform coding development during VVC standardization is presented, and the transform coding tools in the VVC standard are described in detail together with their initial design, incremental improvements and implementation aspects. To improve coding efficiency, four new transform coding techniques are introduced in VVC, which are namely Multiple Transform Selection (MTS), Low-Frequency Non-separable Secondary Transform (LFNST) and Sub-Block Transform (SBT), as well as a large (64-point) type-2 DCT. The experimental results on VVC reference software (VTM-9.0) show that average 4.5% and 3.6% overall coding gain can be achieved by the VVC transform coding tools for All Intra and Random Access configurations, respectively.

Section: A Primary Transformmentioning

confidence: 99%

Transform Coding in the VVC Standard

Kim

IEEE Trans. Circuits Syst. Video Technol.

et al. 2021

IEEE Trans. Circuits Syst. Video Technol.

“…The concept of separable transforms competition has been widely investigated for HEVC [17], [18] which considers only DCT-II along with DST-VII for Intra luma blocks of size 4×4 [19], and then integrated in the JEM software [10]. This latter enables five trigonometrical transform types including DCT-II, V and VIII, and DST-I and VII.…”

Section: A Multiple Transform Selection In Vvcmentioning

confidence: 99%

“…In this section the C N 2 corresponds to the N-point DCT-II matrix with N ∈ {4, 8, 16, 32}. The DCT-II and IDCT-II N-point kernels are computed by Equations (18) and (19), respectively…”

Section: A Unified Forward and Inverse Dct-ii Core Transformmentioning

confidence: 99%

“…From equations (18) and (19), and benefiting from butterfly decomposition architecture, the difference between DCT-II and IDCT-II is the hierarchical application of the associate butterfly block; as a first or last stage for forward and inverse processes, respectively, depending on Forward-Inverse selection signal. For the IDCT [C 32 2 ] T computation, the 32-odd part is computed as O 16 .…”

Section: A Unified Forward and Inverse Dct-ii Core Transformmentioning

confidence: 99%

See 1 more Smart Citation

Forward-Inverse 2D Hardware Implementation of Approximate Transform Core for the VVC Standard

Kammoun

Hamidouche

Philippe

et al. 2020

Self Cite

The future video coding standard named Versatile Video Coding (VVC) is expected by the end of 2020. VVC will enable better coding efficiency than the current High Efficiency Video Coding (HEVC) standard. This coding gain is brought by several coding tools. The Multiple Transform Selection (MTS) is one of the key coding tools that have been introduced in VVC. The MTS concept relies on three transform types including Discrete Cosine Transform (DCT)-II, Discrete Sine Transform (DST)-VII and DCT-VIII. Unlike the DCT-II that has fast computing algorithms, the DST-VII and DCT-VIII rely on more complex matrix multiplication. In this paper an approximation approach is proposed to reduce the computational cost of the DST-VII and DCT-VIII. The approximation consists in applying adjustment stages, based on sparse block-band matrices, to a variant of DCT-II family mainly DCT-II and its inverse. Genetic algorithm is used to derive the optimal coefficients of the adjustment matrices. Moreover, an efficient hardware implementation of the forward and inverse approximate transform module is proposed. The architecture design includes a pipelined and reconfigurable forward-inverse DCT-II core transform as it is the main core for DST-VII and DCT-VIII computations. The proposed 32-point 1D architecture including low cost adjustment stages allows the processing of a video in 2K and 4K resolutions at 1095 and 273 frames per second, respectively. A unified 2D implementation of forwardinverse DCT-II, approximate DST-VII and DCT-VIII is also presented. The synthesis results show that the design is able to sustain a video in 2K and 4K resolutions at 386 and 96 frames per second, respectively, while using only 12% of Alms, 22% of registers and 30% of DSP blocks of the Arria10 SoC platform.

ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

“…block of residuals). The transform competition has been investigated under HEVC standard [16], [17], and more recently under the Joint Exploration Model (JEM) software [18]. The JEM codec defines five trigonometrical transform types including DCT-II, V and VIII, and DST-I and VII.…”

Section: A Separable Transform Modulementioning

confidence: 99%

Lightweight Hardware Implementation of VVC Transform Block for ASIC Decoder

Farhat

Hamidouche

Grill

et al. 2020

Versatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. Compared to its predecessor, VVC introduces new coding tools to make compression more efficient at the expense of higher computational complexity. This rises a need to design an efficient and optimised implementation especially for embedded platforms with limited memory and logic resources. One of the newly introduced tools in VVC is the Multiple Transform Selection (MTS). This latter involves three Discrete Cosine Transform (DCT)/Discrete Sine Transform (DST) types with larger and rectangular transform blocks. In this paper, an efficient hardware implementation of all DCT/DST transform types and sizes is proposed. The proposed design uses 32 multipliers in a pipelined architecture which targets an ASIC platform. It consists in a multi-standard architecture that supports the transform block of recent MPEG standards including AVC, HEVC and VVC. The architecture is optimized and removes unnecessary complexities found in other proposed architectures by using regular multipliers instead of multiple constant multipliers. The synthesized results show that the proposed method which sustain a constant throughput of two pixels/cycle and constant latency for all block sizes can reach an operational frequency of 600 Mhz enabling to decode in real-time 4K videos at 48 fps.