Transformerless quadratic‐based high step‐down DC–DC converter with wide duty cycle range

Abstract

In this study, a quadratic-based transformerless high step-down DC-DC buck converter is presented. There are two switching patterns applied to the switches. Through the first switching pattern, the proposed converter provides a constant stepdown voltage conversion ratio for the whole ranges of duty cycles. On the other hand, by using an interleaved switching pattern for the proposed converter the input voltage will be divided equally between the primary capacitors, as a result, low voltage stress will be across the semiconductor components. This feature allows the designer to select switches and diodes with lower voltage ratings. However, with the interleaved switching pattern, the converter will have two different voltage conversion ratios for duty cycles larger and less than 0.5. Furthermore, the proposed converter is capable of providing a high range of currents without applying extremely narrow duty ratios. Theoretical analysis is provided in this study. To show the merits of the proposed converter, it is compared with other similar recently presented converters. A 430 W prototype of the proposed converter with 600 V/20 V is implemented and experimental results are presented and compared with the theoretical ones.

Analysis and control of a single switch wider step‐down gain DC–DC converter for low‐voltage applications

“…On effective switch utilization front, the presented CLSDC outsmarts TBC 3 and quadratic gain topologies in Palomo et al, 6 Lica et al, 7 and Oliveira et al 16 and maintains close competency with Malanche et al, 15 Chavoshipour Heris et al, 19 Hwu et al, 20 Chuang et al, 21 and Ching‐Tsai et al 22 Having inductor‐fed smoother source current, CLSDC also benefits from lower ripple than the discussed contemporary topologies 7,15,19–22 where extortionate pulsed supply current is unavoidable. As far as L‐C and switching elements are concerned, the presented CLSDC exhibits their lesser count than Chavoshipour Heris et al, 19 Hwu et al, 20 Chuang et al, 21 and Ching‐Tsai et al, 22 whereas it closely follows Malanche et al 15 and Oliveira et al 16 The comparison of stress acting on components, that is, MOSFET switch, power diodes, and inductors in terms of voltage/current quantities, has been shown through Figure 6. Each of these plots depicts CLSDC gradually trending at lesser magnitudes or in near proximity to the counterpart topologies.…”

“…The CLSDC's performance parameters are evaluated against TBC 3 , recent similar kinds of configurations 6,7,15,16,19–22 and duly summarized in Table 4 for reference purpose.…”

“…Further investigations for dependable alternatives evolved semiquadratic gain topologies 8–19 . The step‐down capability of circuits in Hasanpour et al, 8 Veerachary, 9 Lica et al, 10 Uno et al, 11 and Vecchia et al 12 are persistently substandard than quadratic buck converter (QBC), whereas topologies 14–19 struggle to retain modest component count/stress, reasonable efficiency, or less source current ripple. Interleaved structures 20–25 eased output stage current ripple constraint, yet they require proper addressal of current balancing issues.…”

“…Interleaved structures 20–25 eased output stage current ripple constraint, yet they require proper addressal of current balancing issues. In short, the discussed literature 4–25 clearly reveal that source current ripple smoothening and extreme voltage step‐down cannot be achieved unlesssetrestrictions on either circuit elements, wider operating duty ratios, or minimized electric stress on components are relaxed. Hence, aptly striking an optimum balance among these performance factors, a new capacitor–inductor (C–L) charge pump network‐based step‐down converter (CLSDC) is presented through this paper.…”

Simplified cascade multiphase DC-DC buck power converter for low voltage large current applications: part I --- steady-state analysis

“…In the derivation of average output voltage, it is assumed that the voltage drop across the transistor during conduction can be represented as (5) 𝑣 𝑄 = 𝑉 𝑄 + 𝑅 𝑄 𝑖 𝑄 (5) and the voltage drop across the diode during conduction as (6) 𝑣 𝐷 = 𝑉 𝐷 + 𝑅 𝐷 𝑖 𝐷 (6) where V Q is the on-state drop voltage of the active switch, R Q is the on-state drain-to-source resistance, i Q is the current flowing in the switch, V D is diode forward voltage, R D is the diode internal resistance and i D is the current flowing in the diode. The resistances of inductors are assumed the same as R L .…”