Transient bounding in networks with distributed and lumped parameters

Marinov, Corneliu A.

doi:10.1109/81.660746

Cited by 6 publications

(3 citation statements)

References 50 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The delay time bound is an important performance indicator in interconnect circuits (Marinov and Neittaanm 1991, Marinov and Shivakumar 1996, Marinov 1998, Hou et al 2000. Marinov and Shivakumar (1996) defined the global switching time (GST) and obtained the GST bounds of an i?C-ladder network, a basic model used in integrated circuits.…”

Section: Delay Time Bounds For Rc-and Rlc-ce\\ Networkmentioning

confidence: 99%

“…The method via Lanczos process is compared with not only the method by Marinov and Shivakumar (1996) but also with another improved method (Hou et al 2000) in Section 6.4.1. Moreover, in their work (Marinov andShivakumar 1996, Hou et al 2000 ), the precision of numerical results are set at 10" 1 and 10 -4 , respectively. So, the numerical precision is set at 10" 4 in the examples.…”

Section: Numerical Examples and Analysismentioning

confidence: 99%

“…The performance of the network can be described with just a 2 nd -order model. Using the Lanczos algorithm, improved delay bounds compared to other methods (Marinov andShivakumar 1996, Hou et al 2000) can be derived. The jRC-ladder network shown in Figure 6.1 is chosen as the example.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Timing analysis of interconnect networks

Yi¹

View full text Add to dashboard Cite

Timing analysis of high-order networks has been an important issue in system study. The delay is one of the important parameters to characterize a system and can be obtained from the transfer function of the system. With smaller feature sizes and increasing clock frequencies of today's semiconductor technology, interconnections between logic gates may actually be the dominant contributors of delay. In addition, interconnect effects such as ringing, reflection, crosstalk, dispersion and attenuation may corrupt logic signals and degrade system performance. These effects are not always handled appropriately, accurately or efficiently by the present levels of circuit simulators. This thesis is to study and analyze the delay of interconnect structures and various networks containing large linear structures with nonlinear terminations. Approximation methods to compute delays of large interconnect networks are investigated. An approach for systematic interconnect design is to express the system behavior by poles and zeros. However, for a large interconnect network, computations of poles and zeros are extremely time-consuming. The time and accuracy performances of exact methods versus two approximate fast methods, the asymptotic waveform evaluation (AWE) technique and Pade approximation, are compared in evaluating the delays of circuits.

show abstract

Section: Delay Time Bounds For Rc-and Rlc-ce\\ Networkmentioning

confidence: 99%

Section: Numerical Examples and Analysismentioning

confidence: 99%

See 1 more Smart Citation

Timing analysis of interconnect networks

Yi¹

View full text Add to dashboard Cite

show abstract