Transient Radiation Effects in SOI Memories

Davis, G. W.; Hite, L.R.; Blake, T.G.W.; Chen, C.-E.; Lam, Hon Wai; DeMoyer, Robert

doi:10.1109/tns.1985.4334137

Cited by 70 publications

(7 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Unfortunately, as briefly mentioned in Section III, charge deposited in the body region (for example, by a particle strike to the gate region) can trigger a bipolar mechanism that limits the SEU hardness of SOI circuits [64], [65]. Body ties are sometimes used commercially to reduce floating-body effects under dc operation, and careful attention to body tie design is crucial to maintaining good SEU performance [64], [95], [96]. Even in body-tied SOI designs, manufacturers have found it necessary to incorporate other hardening methods for applications where very high upset thresholds are desired [93], [97], [98].…”

Section: A Technology Hardeningmentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

901

427

View full text Add to dashboard Cite

Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

show abstract

Section: A Technology Hardeningmentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

901

427

View full text Add to dashboard Cite

show abstract

“…The first paper on the transient response of SOI CMOS SRAMs found larger than expected photocurrents, and briefly conjectured on the possibility of conduction through the buried oxide before determining that the cause of the excess current was the now well-known parasitic bipolar effect [26]. CMOS/SOS heavy ion experiments showed that charge deposited in the sapphire substrate was not collected in the silicon layer, and that the SEU-sensitive area in CMOS/SOS SRAMs could be attributed entirely to gate strikes [24], [27].…”

Section: A Charge Collection Mechanisms In Soimentioning

confidence: 99%

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Dodd

Shaneyfelt

Horn

et al. 2001

IEEE Trans. Nucl. Sci.

177

View full text Add to dashboard Cite

Large-scale three-dimensional (3-D) device simulations, focused ion microscopy, and broadbeam heavy-ion experiments are used to determine and compare the SEU-sensitive volumes of bulk-Si and SOI CMOS SRAMs. Single-event upset maps and cross-section curves calculated directly from 3-D simulations show excellent agreement with broadbeam cross section curves and microbeam charge collection and upset images for 16 K bulk-Si SRAMs. Charge-collection and single-event upset (SEU) experiments on 64 K and 1 M SOI SRAMs indicate that drain strikes can cause single-event upsets in SOI ICs. 3-D simulations do not predict this result, which appears to be due to anomalous charge collection from the substrate through the buried oxide. This substrate charge-collection mechanism can considerably increase the SEU-sensitive volume of SOI SRAMs, and must be included in single-event models if they are to provide accurate predictions of SOI device response in radiation environments.

show abstract

“…Silicon on Insulator (SOI) technologies have been studied from late 80's [1][2][3][4] by defense agencies for their intrinsic hardness towards radiations especially their Single Event Latchup (SEL) immunity as well as reduced Single Event Upset (SEU) effects [5][6] compared to their bulk counterparts. These early Partially Depleted SOI technologies main process features are thick active silicon and thick Buried Oxide.…”

Section: Introductionmentioning

confidence: 99%