Transistor-level based defect tolerance for reliable nanoelectronics

Al-Hashimi, Bashir M.; Melouki, Aissa

doi:10.1109/aiccsa.2008.4493516

Cited by 8 publications

(4 citation statements)

References 14 publications

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“…The quadded‐transistor (QT) technique is proved to be more efficient than QL method in terms of area and reliability [10]. In QT, four transistors replace a single transistor and because of proper ordering arrangement of the transistors, QT is capable of handling any single defect.…”

Section: Limitations Of the Existing Sr Methodsmentioning

confidence: 99%

“…Static techniques, also called as defect tolerant methods, are robust, non‐adaptive in nature and effectively mask both permanent and transient types of faults. All modules including the redundant spares are active and powered on simultaneously in case of static approaches [1–15] whereas in dynamic recovery technique (also known as defect avoidance method), spare modules are activated only upon identification of failure of currently active modules, but the approach cannot recover from transient defects if not identified upon testing [16–19].…”

Section: Introductionmentioning

confidence: 99%

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Fault tolerant architecture design using quad‐gate‐transistor redundancy

Mukherjee¹,

Dhar²

2015

IET Circuits, Devices & Systems

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In the current era of speed and recent trend of device miniaturisation, failure rates have been increased with the increase in the design complexity and the density of transistors in chip and hence reliability issues at circuit level have become more prominent and challenging. In this study, the authors propose a new static fault tolerant method called quad-gate-transistor, which uses quadded-transistor output logic with gate level quad implementation of the given circuitry to make the system defect tolerant. Such combination of gate and transistor level redundancy provides significantly higher reliability over classical triple modular redundancy and other existing static approaches as supported by extensive simulation results using some of the ISCAS 85 benchmark and other standard circuits. The proposed method also takes care of most of the limitations that restrict the use of the existing static methods in practical applications.

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Section: Limitations Of the Existing Sr Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fault tolerant architecture design using quad‐gate‐transistor redundancy

Mukherjee¹,

Dhar²

2015

IET Circuits, Devices & Systems

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“…As a generalisation, this work considers two types of transistor fault: conducting and insulating. These are commonly used in similar literature, being called stuck-closed and stuck open defects amongst other things [7].…”

Section: A Fault Injectionmentioning

confidence: 99%

A hierarchical fault tolerant system on the PAnDA device with low disruption

Lawson

Walker

Trefzer

et al. 2014

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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This paper presents the concept of hierarchical reconfiguration strategies that can be applied to a circuit on a reconfigurable architecture to change the implementation without changing the functionality, and their use to overcome faults in a source agnostic way. The Programmable Analogue and Digital Array (PAnDA) is a novel FPGA-like reconfigurable architecture, with configuration options below the digital layer. The PAnDA architecture includes symmetry and homogeneity at multiple levels of the configuration hierarchy. These properties could be exploited to take advantage of redundant resources in the event of a fault. To demonstrate this, faults are injected, repeatedly and at random, to a configured logic function until functionality breaks. Reconfiguration strategies are then applied at random in repeated steps to the faulty circuit until functionality is restored (or a set number of steps have been taken). An experiment is conducted to investigate whether controlling the probability of picking a particular strategy at each step can improve the average efficiency of fault recovery for a given function. It is found that the average number of steps required to fix a fault can be reduced while it is possible to increase the average number of circuits that can be fixed.

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“…Device (transistor) level redundancy schemes have been proposed since the 1990s [16–19], including threshold logic gates [20–28], extrapolating quadded logic [29] to the device level [30–32], as well as for nanotechnologies [33–38]. All of these are alternative approaches to gate and circuit/system level redundancy schemes, and aim to achieve reliable computation by improving on the switching error probabilities of the devices (transistors) and enhancing gates’ noise immunities and their tolerance to variations.…”

Section: Introductionmentioning

confidence: 99%