Transistor-Level Based Defect-Tolerance for Reliable Nanoelectronics

Abstract

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by quaddedtransistor structure that guarantees defect tolerance of all single defects and a large number of multiple defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to 4 to 5 times more transistor defect probability) and at reduced area overhead.

A Fault Tolerant Voter for Approximate Triple Modular Redundancy

“…The proposed design, with 18 transistors, outperforms all other designs in terms of the delay, power, and power-delay-product (PDP). There are four quad structures present in the design where each quad structure has an effective resistance equal to that of a single transistor [19]. The proposed design basically involves six effective resistances which is minimum among all existing works and enables the design to have the least delay compared to all the other voters.…”

“…An input stuck-at-0 (s-a-0) fault at a PMOS transistor results in a closed path between the drain and source. References [19,20] proposed the use of Quadded Transistor redundancy and Triple Transistor redundancy, respectively, for the provisioning of input fault tolerance. For the proposed voter faults, flipping of the inputs of the voter is handled using the redundancy technique of [19].…”

“…References [19,20] proposed the use of Quadded Transistor redundancy and Triple Transistor redundancy, respectively, for the provisioning of input fault tolerance. For the proposed voter faults, flipping of the inputs of the voter is handled using the redundancy technique of [19]. As the number of transistors is kept to a minimum using pass transistors, unlike in previous studies, this provides us with the freedom to introduce transistor-level redundancy for the voter inputs.…”

“…Two such structures are then connected in series (A + A)(A + A). This configuration of quad transistor is opted because each quad structure has an effective resistance equal to that of a single transistor [19]. Hence, a quadded structure implements the logic function (A + A)(A + A) and (B + B)(B + B) for A and B inputs, respectively, in the proposed voter, as shown in Figure 4e.…”

“…Double s-a-1 (NMOS)/s-a-0 (PMOS) are tolerated if they do not occur in any two series transistors. In addition, any triple fault that does not include two parallel s-a-0 (NMOS)/s-a-1 (PMOS) transistors or two series s-a-1 (NMOS)/s-a-0 (PMOS) transistors is tolerated [19]. The proposed voter design is presented in Figure 4e.…”