Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Switching

Li, Zhentao; Chen, Shuming

doi:10.1109/cadcg.2007.4407901

Cited by 5 publications

(2 citation statements)

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“…In Static Timing Analysis (STA), the modeling of the delay time has always focused on models that represent gates as black boxes, without calculating the accurate internal waveforms. The STA calculates the gate delay approximately using look-up table and equations include the transistors sizes, the load capacitance and input ramps [2]. Most models in literature fall into this category.…”

Section: Background and Definitionsmentioning

confidence: 99%

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Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits

Rjoub

Alajlouni

2013

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The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.

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Section: Background and Definitionsmentioning

confidence: 99%

“…It calculates approximately the gate delay using look-up table or linear equations. However, exist-ing delay models become less accurate in nanometer circuits, because of the growing interactions between nodes [2].…”

Section: Introductionmentioning

confidence: 99%