Transistor realization of reversible “ZS” series gates and reversible array multiplier

Zhou, Ri-Gui; Shi, Yang; Wang, Hui'an; Cao, Jian

doi:10.1016/j.mejo.2010.11.008

Cited by 26 publications

(13 citation statements)

References 26 publications

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“…We found that the recent publication on multiplier in [38] discussed N xN reversible multiplier design. We considered the designs proposed in [38,39] and compared it with our work, as the efforts in both of these papers were to reduce the number of constant inputs and garbage outputs.…”

Section: Fredkin Gate (Frg)mentioning

confidence: 99%

“…Hence, we compared our design with other N xN reversible designs that are available in the literature. The designs proposed in [38] and [39] show the calculation for N xN reversible multiplier. In both of these papers, the authors have shown only the ancilla inputs and garbage outputs calculations; the comparisons shown in Tables I, II list only ancilla inputs and garbage outputs for these papers.…”

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

“…Our proposed design showed a better improvement in terms of the ancilla inputs resulting in saving the chip area since the number of lines are reduced. We have listed the garbage outputs of the designs proposed in [38] and [39]. Our design outperforms the existing designs because it is 100% better in terms of garbage outputs since our design produces no garbage.…”

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

“…We compared our design with another garbageless reversible multiplier design using the recursive scheme in [40]. Here, we compare our work with [38], [3]-R.Zhou et.al [39] Karatsuba multiplier design presented in [40]. The comparison for gate count, ancilla inputs, and delay are shown in Table III.…”

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

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Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

et al. 2016

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Abstract-A reversible logic has application in quantum computing. A reversible logic design needs resources such as ancilla and garbage qubits to reconfigure circuit functions or gate functions. The removal of garbage qubits and ancilla qubits are essential in designing an efficient quantum circuit. In the literature, there are multiple designs that have been proposed for a reversible multiplication operation. A multiplication hardware is essential for the circuit design of quantum algorithms, quantum cryptanalysis, and digital signal processing (DSP) applications. The existing designs of reversible quantum integer multipliers suffer from redundant garbage qubits. In this work, we propose a reversible logic based, garbage-free and ancilla qubit optimized design of a quantum integer multiplier. The proposed quantum integer multiplier utilizes a novel add and rotate methodology that is specially suitable for a reversible computing paradigm. The proposed design methodology is the modified version of a conventional shift and add method. The proposed design of the quantum integer multiplier incorporates add or no operation based on multiplier qubits and followed by a rotate right operation. The proposed design of the quantum integer multiplier produces zero garbage qubits and shows an improvement ranging from 60% to 90% in ancilla qubits count over the existing work on reversible quantum integer multipliers.

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Section: Fredkin Gate (Frg)mentioning

confidence: 99%

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

Section: Performance Parameters Of Nxn Reversible Multiplier Blockmentioning

confidence: 99%

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Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

et al. 2016

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“…To figure result of two marked numbers we have utilized adjusted Baugh-Wooley approach [8]. Both legitimate and reversible multiplier outline is partitioned into two sections: fractional item era circuit and after that multi-operand expansion circuit.…”

Section: Reversible Multipliermentioning

confidence: 99%

A Novel VLSI Design of Sign and Unsigned Irreversible and Reversible Multiplier Circuit

Mishra¹,

Abdullah²

2015

IJCA

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Reversible rationale is all that much sought after for the future figuring advancements as they are known not low power dissemination having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and picture preparing. Adders and multipliers are fundamental building blocks in many computational units. In this paper we have presented and implemented irreversible and reversible Baugh Wooley approach using standard irreversible and reversible logic gates/cells. The problem of minimizing the number of garbage outputs is an important issue in reversible logic design. It is proved that the proposed multiplier is better and optimized, compared to its existing counterparts with respect to the number of gates, constant inputs, garbage outputs and number of transistors required.

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2020

Reversible and DNA Computing

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Transistor realization of reversible “ZS” series gates and reversible array multiplier

Cited by 26 publications

References 26 publications

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

A Novel VLSI Design of Sign and Unsigned Irreversible and Reversible Multiplier Circuit

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