Transistor size optimization in the tailor layout system

Abstract

This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound on circuit delay is achieved. All delay paths are considered by modeling circuit delay with a logic independent delay graph. Tailor's optimizer globally optimizes circuit area (in one dimension) and delay by use of compaction and nonlinear programming algorithms. The optimizer does not yet optimize in two dimensions simultaneously or optimize hierarchical circuits. Results for a few optimized CMOS circuits are presented.

Transistor Sizing of Energy-Delay-Efficient Circuits

“…Classical numerical methods, such as the conjugate gradient descent method, have been applied to the transistor-sizing problem: there exist several transistor sizing programs that minimize power consumption while maintaining performance specifications [5,6,7]. More recently, several specialized numerical techniques have been proposed [8,9,10].…”

Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint

“…W N = NW 1 (11) where W N is the power optimal width of a series of N MOSFETS and W 1 is the power optimal size of an inverter. Using 1.2 micron technology, the results for a two and three input NOR gates are compared with that of an inverter in gure 3.…”

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization

“…Gate and transistor sizing have been studied in great detail in the past [2,3,4] for technologies in which gate delays dominate the overall path delay. With the increasing role of interconnect, timing-driven placement approaches [5] have been proposed with a view toward minimizing the interconnect * This work was supported in part by the Semiconductor Research Corporation under contract 94-DJ-343, the National Science Foundation under contract MIP-9157263, and IBM Corp.…”

“…In a gate-delay dominated environment, it is well known [3,4] that while increasing the size of a gate may reduce its delay, it increases the delay of the previous stage because of the increased capacitive load. However, in an interconnectdelay dominated circuit the additional circuit-level effects described above need to be considered too.…”