No abstract

This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound on circuit delay is achieved. All delay paths are considered by modeling circuit delay with a logic independent delay graph. Tailor's optimizer globally optimizes circuit area (in one dimension) and delay by use of compaction and nonlinear programming algorithms. The optimizer does not yet optimize in two dimensions simultaneously or optimize hierarchical circuits. Results for a few optimized CMOS circuits are presented.

No abstract

A bs t r ac t This paper describes a new FPGA architecture which relies on a proprietary antifuse technology coupled with 0.8 micron CMOS technology. In this architecture, individual CMOS transistors, not just logic blocks, can be configured to match MPGA macrocells transistor for transistor. Small mux like blocks are also available for logic or latch functions or collectively as configurable static RAMS. The architecture supports macrocell libraries with delay and resource usages similar to commercial 1.5 micron MPGA libraries.