Transition-by-transition FSM traversal for reachability analysis in bounded model checking

Abstract

In bounded model checking (BMC)-based verification flows lack of reachability constraints often leads to false negatives. At present, it is daily practice of a verification engineer to identify the missing reachability constraints by manually inspecting the design code and by analyzing counterexamples. This, unfortunately, requires a lot of effort and is prone to errors. We propose an algorithm to determine reachability constraints automatically. The proposed approach applies to a design style where the operation of the design is controlled by a main FSM which can easily be extracted from the RTL description of the circuit. The algorithm decomposes and analyzes the state space of the circuit by considering transitions of the main FSM. Experimental results show that the proposed method can considerably reduce the manual work of verification engineers.

Auxiliary state machines + context-triggered properties in verification

“…A survey [Shyam and Bertacco 2006] of these approaches shows that a wide range of techniques, ranging from theorem-proving and abstraction-guided counterexample search to symbolic/logic simulation and ATPG-based methods have been employed. The work in Shyam and Bertacco [2006] and Nguyen et al [2005] is most closely related to our approach. In both of these, the specification consists of properties only, unlike in our case where auxiliary state machines are present.…”

“…Our approach is different from STE-based approaches in view of the auxiliary state machines and the verification methodology adopted. Nguyen et al [2005] present a method for extracting reachability constraints to avoid false negatives in a bounded model checking setting. Their approach applies to a design style where the implementation of the design is a main FSM and a set of sub-FSMs.…”

“…We also present a very effective semi-formal approach for such specifications which can be easily developed on top of existing bug-hunting formal/semi-formal verification methods. -We do not assume any particular implementation style, as in Cho et al [1993] and Nguyen et al [2005]. The auxiliary state machine is considered as a part of the formal specification.…”

Property-Driven Partitioning for Abstraction Refinement

“…For hardware, the abstraction is typically partitioned according to the design that usually is composed of submodules (see, e.g., [3,14]). For software, the partitioning is guided by the control-flow graph of the program.…”