Transition test generation using replicate-and-reduce transform for scan-based designs

Abadir, Magdy S.; Zhu, Juhong

doi:10.1109/vtest.2003.1197629

Cited by 5 publications

(2 citation statements)

References 8 publications

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“…A replicate and reduced circuit transform maps the two-time frame processing of the transition fault ATPG to a single-time frame processing on duplicated iterative blocks with reduced connections. Abadir and Zhu [17] report high transition fault coverage using this ATPG method.…”

Section: A Prior Workmentioning

confidence: 92%

See 1 more Smart Citation

Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers

Ahmed¹,

Tehranipoor²,

Ravikumar³

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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At-speed testing is becoming crucial for modern very-large-scale-integration systems, which operate at clock speeds of hundreds of megahertz. In a scan-based test methodology, it is common to use a transition delay fault model for at-speed testing. The launching of the transition can be done either in the last cycle of scan shift [launch-off-shift (LOS)], or in a functional launch cycle that follows the scan shift and precedes the fast capture [launch-off-capture (LOC)]. The LOS technique offers significant advantages over the LOC in terms of coverage and pattern count, but since it requires the scan enable (SEN) signal to change state in the time period of one functional clock cycle, considerable engineering resources are required to close the timing on the SEN signal. Low-cost testers will not be able to provide the at-speed SEN signal as required by the LOS technique. We propose a scan-based at-speed methodology that generates "local" SEN signals that are guaranteed to switch in one functional clock cycle even when the external SEN signal does not change state at functional speed. Our technique is based on encapsulating the SEN control signal in the scan test data. A new scan cell, which is called the last transition generator, must be inserted in every scan chain for generating internal SEN signals. The proposed method is robust, practical, and readily implemented using commercial tools available today.Index Terms-Launch-off-capture (LOC), launch-off-shift (LOS), low-cost tester, scan enable signal (SEN), transition delay fault testing.

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Section: A Prior Workmentioning

confidence: 92%

“…A transition fault ATPG methodology flow for scan-based designs using broadside (LOC) test format is proposed in [17]. A replicate and reduced circuit transform maps the two-time frame processing of the transition fault ATPG to a single-time frame processing on duplicated iterative blocks with reduced connections.…”

Section: A Prior Workmentioning

confidence: 99%