Translating system specifications to VHDL

Narayan, Sanjiv; Vahid, Frank; Gajski, Daniel D.

doi:10.1109/edac.1991.206432

Cited by 23 publications

(4 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We have developed VHDL translators for BIF (described in Section 4.2) [DuCH91] and SpecCharts (described in section 4.3) [NaVG91]. We found that automatically-generated code is a bit larger in size and less elegant than manu ally written code but completely readable and quite satisfactory for simulation.…”

Section: Vhdl Translatorsmentioning

confidence: 99%

Essential Issues and Possible Solutions in High-Level Synthesis

Gajski

1991

High-Level VLSI Synthesis

View full text Add to dashboard Cite

Wrong Trend vs. Wrong Focus CAD technology has been very successful in the last ten years. CAD tools for layout and logic design have been exceptionally successful to the point that they dominate system and chip design methodologies throughout the industry in the U.S. and abroad. This widespread methodology consists of manually refining product specifications through system and chip architecture until the design is finally captured on the logic level and simulated. Standard-cell methodology and tools were developed for easy rnapping of logic-level design into IC layout. Because of the huge investment in CAD tools, equipment and training, many people believe that this trend will continue by providing more sophisticated CAD tools for capture, simulation and synthesis of logic-level designs. Logic level, however, is not a natural level for system designers. For example, when we want to indicate that 32-bit values of two variables, a and 6, should be added and stored in the third variable, c, we simply write the expression c = a + 6. We do not write 32 Boolean expressions with up to 64 variables each to indicate this simple operation. It is very difficult to imagine having complex multi-chip systems described in terms of.l million or more Boolean equations. If we equate layout-level of abstraction (transistors, wires and contacts) with machine-level programming then logic-level (gates, fiip-fiops and finite-state machines) can be equated with assembly-level programming. We know that complex software systems consisting of 1 million or more lines of code are not written in assembly language. Similarly,a complexhardware system of 1 million or more gates should not be captured, simulated or tested on the logic level of

show abstract

Section: Vhdl Translatorsmentioning

confidence: 99%

Essential Issues and Possible Solutions in High-Level Synthesis

Gajski

1991

High-Level VLSI Synthesis

View full text Add to dashboard Cite

show abstract

“…It also includes a parser and a large set of query and miG nipulation routines for use by synthesis tools. Simulation is via automatic translation to VHDL [9], which has also been implemented.…”

Section: Draco Simulationmentioning

confidence: 99%

“…Arbiter Synthesis involves addition of arbiters to resolve bus contention created by interface synthesis. A VHDL Generator [9] allows the designer to verify the functionality of the design at any stage of system level synthesis by converting the SpecChart language to VHDL and simulating using commercial VHDL simulators. It also provides a path to chip level synthesis tools -the individual chip VHDL descriptions obtained as a result of the above synthesis tasks are input to the VHDL Synthesis System [lo] to synthesize each chip separately.…”

Section: Pymentioning

confidence: 99%

System Level Specification and Synthesis

Narayan

Vahid²,

Gajski³

The Fifth International Conference on VLSI Design

Self Cite

View full text Add to dashboard Cite

The need has evolved for a synthesis tool at the computer system level. Currently no tools are available to designers which would allow them to specify the behavior of entire systems and obtain multi-chip designs from those specifications. Essential tasks at the system level include capturing a system's specification, partitioning the specification into chips, synthesizing interfaces between the chips and evaluating the quality and correctness of the design with the help of estimation and simulation tools. The essential components of the SpecSyn system level design environment are presented. The Speccharts language, which has been developed for specifying system level designs, is introduced. Basic issues in system specification and synthesis are illustrated with the help of a simple computer example and an industrial design.

show abstract

“…Simulation is usually carried out by translating the specification into VHDL or C. StateCharts [4], Structured Analysis (SA) [5] and SpecCharts [6] are examples of graphical source languages.…”

Section: Introductionmentioning

confidence: 99%