Translation Validation of Code Motion Transformations Involving Loops

Chouksey, Ramanuj; Karfa, Chandan; Bhaduri, Purandar

doi:10.1109/tcad.2018.2846654

Cited by 7 publications

(7 citation statements)

References 10 publications

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“…In this experiment, we compare the VP_TT with the VP method [9], EVP method [24] and the VP_TT_static method. The EVP method is an enhanced version of the VP method and capable of handling the scenario which involves loop invariant code motion.…”

Section: F I G U R E 7 the Overall Flow Of Our Verification Methodsmentioning

confidence: 99%

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VP_TT: A value propagation based equivalence checker for testability transformations

2021

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Testability transformation (TT) is a source-to-source programme transformation that aims to improve the ability of a given test generation method to generate test data for the original programme. Herein, the correctness of testability transformations is shown. Translation validation is the process of proving that the transformed programme is a correct translation of the source programme being compiled. It is widely used to verify the correctness of various compiler optimizations and transformations during scheduling. The value propagation based equivalence checking (VP) method is an efficient translation validation approach proposed to verify the correctness of various compiler optimization applied during scheduling in high-level synthesis. VP-based translation validation of testability transformations is proposed. In particular, it is identified that the existing VP method fails to show the equivalence for some of the TTs. A dynamic cutpoint selection scheme and an enhancement to the VP method to overcome these limitations are shown. The enhanced VP method, called VP_TT, successfully shows the equivalence for the TTs where the VP method fails. Experimental results confirm the usefulness of VP_TT in the verification of testability transformations.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: F I G U R E 7 the Overall Flow Of Our Verification Methodsmentioning

confidence: 99%

“…The VP method is enhanced in Ref. [24] to handle code motion involving loops. An counter example generation process using SMT solver in case of non‐equivalence shown by VP method is shown in Ref.…”

Section: Related Workmentioning

confidence: 99%

VP_TT: A value propagation based equivalence checker for testability transformations

2021

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“…The paper [15] enhances the VP method to handle the false computation and code motion transformation involving loops.…”

Section: Related Workmentioning

confidence: 99%

“…The paper [12] enhances the VP method, so that code motions of array‐intensive behaviours can be validated. The paper [15] enhances the VP method to handle the false computation and code motion transformation involving loops.…”

Section: Related Workmentioning

confidence: 99%

“…Many path-based approaches have been proposed for verification of HLS [3,4,7,[9][10][11][12][13][14][15], where each behaviour is represented by a finite state machine with datapath (FSMD) [16]. In general, path-based approaches decompose each FSMD into a finite set of finite paths and the equivalence of FSMDs is established by showing path level equivalence between two FSMDs.…”

Section: Introductionmentioning

confidence: 99%

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Counter‐example generation procedure for path‐based equivalence checkers

et al. 2019

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Path-based equivalence checkers (PBECs) have been successfully applied for verification of programmes from diverse domains and from various stages of high-level synthesis. In the case of non-equivalence, PBEC provides very little information which is not sufficient for further investigation of the two programmes being compared by some human expert. In this work, the authors show how a counter-trace (cTrace) can be generated in the case of non-equivalence reported by the PBEC. Using this cTrace, they also present a procedure to find suitable initialisation values for input variables which reveal the non-equivalence (i.e. counterexample) by using off-the-shelf satisfiability modulo theories (SMT) solvers. To aid the human expert, they also show that how they can visualise this cTrace in the control and data-flow graph of the programmes using the graph visualisation software-Graphviz. This counterexample and visual representation of the corresponding cTrace will be helpful in debugging the root cause of the non-equivalence. The experimental results are encouraging.

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