Translation Validation of High-Level Synthesis

Abstract

Abstract-The growing complexity of systems and their implementation into silicon encourages designers to look for ways to model designs at higher levels of abstraction and then incrementally build portions of these designs-automatically or manually-from these high-level specifications. Unfortunately, this translation process itself can be buggy, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. Therefore, checking if the implementation is a refinement or equivalent to its initial specification is of tremendous value. In this paper, we present an approach to automatically validate the implementation against its initial high-level specification using insights from translation validation, automated theorem proving, and relational approaches to reasoning about programs. In our experiments, we first focus on concurrent systems modeled as communicating sequential processes and show that their refinements can be validated using our approach. Next, we have applied our validation approach to a realistic scenario-a parallelizing high-level synthesis framework called Spark. We present the details of our algorithm and experimental results.

Source Code Error Detection in High-Level Synthesis Functional Verification

“…Formal methods have been applied to verify the HLS process using translation validation. For example, Ashar et al [27] focused on the valid binding stage of HLS, while recently [26] focused on the scheduling and concurrent systems modeling communicating sequential processes. Formal methods have gained popularity because RTL simulations for larger designs, simulations are too slow and cannot detect corner cases.…”

Formal verification of code motion techniques using data-flow-driven equivalence checking

“…Any software of this scale is prone to logical and implementation errors. For instance, two bugs have recently been identified in the widely used HLS tool SPARK [Gupta et al 2003b] by the method proposed in Kundu et al [2010]. This demonstrates that verification of the HLS process can catch bugs that even testing and long-term use may not uncover.…”

“…This demonstrates that verification of the HLS process can catch bugs that even testing and long-term use may not uncover. Despite the fact that a significant amount of work has been carried out for verification of HLS steps, the state-of-the-art techniques are still far from being able to prove automatically that the HLS process always produces correct RTL designs [Kundu et al 2010]. The problem of verifying the HLS tools is the same as that of proving programs to be correct which is difficult and is not pursued.…”

“…These techniques are not applicable to the verification of code motions since code may be moved from one basic block to other basic blocks due to code motions. Some recent works, such as Karfa et al [2008], Kim and Mansouri [2008], and Kundu et al [2008Kundu et al [ , 2010 target verification of code motion techniques. Specifically, a path-recomposition-based FSMD equivalence checking has been reported in Kim and Mansouri [2008] to verify speculative code motions.…”

synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs

“…In response to these criticisms, there are several efforts that extend C-like languages with constructs to express parallel computation [2], [8], timing models [2], and that integrate formal methods [9]. For example, Handel-C extends C with a par construct for explicit parallelism, and Kiwi [8] leverages the concurrency mechanism in .NET for parallel specifications.…”