Transport properties in silicon nanowire transistors with atomically flat interfaces

Liu, F.; Husain, Muhammad; Li, Z.; Sotto, Moise; Burt, Daniel; Fletcher, J. D.; Kataoka, M.; Tsuchiya, Yoshishige; Saito, Shinichi

doi:10.1109/edtm.2017.7947561

Cited by 1 publication

(1 citation statement)

References 8 publications

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“…It is based on a one-dimensional silicon channel on top of a fully-depleted silicon-on-insulator wafer and exhibits a back-gate, two TiN side-gates, and an array of thin TiN top-gates. In contrast to the modified FinFET devices of [24,25,27], the channel is anisotropically wet-etched by tetramethylammonium hydroxide (TMAH), which results in a trapezoidal nano-ridge with atomically-flat {111} facets [30,31]. The angle of the tip of the trapezoidal nano-ridge can be further tuned by the local-oxidation of silicon (LOCOS) process of the {111} silicon facets.…”

Section: Device Conceptmentioning

confidence: 99%

Spin Qubits Confined to a Silicon Nano-Ridge

et al. 2019

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Electrostatically-defined quantum dots (QDs) in silicon are an attractive platform for quantum computation. Localized single electron spins define qubits and provide excellent manipulation and read-out fidelities. We propose a scalable silicon-based qubit device that can be fabricated by industry-compatible processes. The device consists of a dense array of QDs localized along an etched silicon nano-ridge. Due to its lateral confinement, a simple dense array of metallic top-gates forms an array of QDs with controllable tunnel-couplings. To avoid potential fluctuations because of roughness and charged defects at the nano-ridge sidewall, the cross-section of the nano-ridge is trapezoidal and bounded by atomically-flat {111} facets. In addition to side-gates on top of the low-defect oxidized {111} facets, we implement a global back-gate facilitated by the use of silicon-on-insulator. The most relevant process modules are demonstrated experimentally including anisotropic wet-etching and local oxidation of the silicon nano-ridge, side-gate formation with chemical-mechanical polishing, and top-gate fabrication employing the spacer process. According to electrostatic simulations, our device concept allows forming capacitively-coupled QD double-arrays or adjacent charge detectors for spin-readout. Defining a logical qubit or realizing a single electron conveyor for mid-range qubit-coupling will be future applications.

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