Trap-Assisted Passing Word Line Leakage and Variable Retention Time in DRAM

Sun, Yumeng; Liu, Xiang; Wang, Noakim; Jeon, Jongsung; Wu, Blacksmith; Cao, Kanyu

doi:10.1109/icet51757.2021.9451059

Cited by 7 publications

(1 citation statement)

References 12 publications

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“…Nevertheless, as the device size of DRAM decreases, it simultaneously generates various types of leakage currents, hindering DRAM performance. Leakage currents, such as gate-induced drain leakage (GIDL), gate-induced function leakage, 1-row hammer, and PGE, are recognized factors in the decline in DRAM performance [1][2][3][4][5][6][7][8][9][10][11]. GIDL and GIJL specifically impact individual DRAM cells, influencing a single bit at a time.…”

Section: Introductionmentioning

confidence: 99%

Mitigating WL-to-WL Disturbance in Dynamic Random-Access Memory (DRAM) through Adopted Spherical Shallow Trench Isolation with Silicon Nitride Layer in the Buried Channel Array Transistor (BCAT)

Kim,

Lim,

Kwon

2024

Electronics

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The Pass Gate Effect (PGE), often referred to as adjacent cell interference, presents a significant challenge in dynamic random-access memory (DRAM). In this study, we investigate the impact of PGE and propose innovative solutions to address this issue in DRAM technology, employing 10 nm node technology with buried channel array transistors. To evaluate the efficacy of our proposals, we utilized SILVACO for simulating various DRAM configurations. Our approach centers on two key structural optimizations: the introduction of a spherical Shallow Trench Isolation (STI) and the incorporation of a silicon nitride (Si3N4) layer within the spherical STI structure. These optimizations were meticulously designed to mitigate the PGE by considering several factors that are highly influential in its manifestation. To validate our approach, we conducted comprehensive simulations, comparing the PGE factors of typical DRAM structures with those of our proposed configurations. The results of our analysis strongly support the effectiveness of our proposed structural enhancements in alleviating the PGE when contrasted with conventional DRAM structures. Remarkably, our optimizations achieved a remarkable 82.4% reduction in the PGE, marking a significant breakthrough in the field of DRAM technology. By addressing the PGE challenge and substantially reducing its impact, our research contributes to the advancement of DRAM technology, offering practical solutions to enhance data integrity and reliability in the era of 10 nm node DRAM.

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