2015
DOI: 10.1002/pssa.201431744
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Trapping mechanisms in GaN‐based MIS‐HEMTs grown on silicon substrate

Abstract: In this work we report on the three dominant trapping mechanisms affecting the dynamic performance of a double-heterostructure GaN-based MIS-HEMT grown on silicon substrate. In the OFF-state, with high drain voltage and pinched-off 2DEG, the dominant mechanism is the charge-trapping in the gate-drain access region caused by the transversal drain-to-substrate potential. This effect causes the dynamic increase of the ON-resistance, and is positively temperature-dependent, thus of great concern for high-temperatu… Show more

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Cited by 72 publications
(35 citation statements)
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“…[13][14][15] However, the electronic states existing at such interfaces may significantly influence the device performance due to uncontrolled interface charging. [16][17][18][19][20][21][22][23] Despite the high importance of interface states at dielectric/III-N heterojunction interfaces, their origin and properties, in particular, the density distribution vs. energy, D it (E), in the wide band gap, E G , and charge type (donor-like or acceptor-like) are still not clarified. The main reason of such a situation are the extreme obstacles in the quantitative characterization of interface states by means of the electrical methods in the case of III-N heterojunction based devices because of the presence of two interfaces and very long time constants for charge emission from the deep states at room temperature (RT).…”
Section: Introductionmentioning
confidence: 99%
“…[13][14][15] However, the electronic states existing at such interfaces may significantly influence the device performance due to uncontrolled interface charging. [16][17][18][19][20][21][22][23] Despite the high importance of interface states at dielectric/III-N heterojunction interfaces, their origin and properties, in particular, the density distribution vs. energy, D it (E), in the wide band gap, E G , and charge type (donor-like or acceptor-like) are still not clarified. The main reason of such a situation are the extreme obstacles in the quantitative characterization of interface states by means of the electrical methods in the case of III-N heterojunction based devices because of the presence of two interfaces and very long time constants for charge emission from the deep states at room temperature (RT).…”
Section: Introductionmentioning
confidence: 99%
“…Consequently, in the studies and modeling of the operation of IG-type GaN-based HEMTs, the capture cross section values typical for the SiO 2 /Si interface or bulk defect levels are often inadequately assumed. [18][19][20][21][22][23] The aim of the present work is the determination and analysis of the electron capture cross sections (r) of interface states at dielectric/III-N heterojunction interfaces using a newly developed photo-electric method. This method is based on the measurement of the threshold voltage shift (᭝V th ) in a capacitance-voltage (C-V) characteristics before and after illumination using photon energies (E ph ) less than the band gap (E g ) at high temperature (T).…”
Section: Introductionmentioning
confidence: 99%
“…As in the case of normally-off transistors, the exposure to high drain bias in the off-state can trigger further trapping processes, due to the filling of surface states [8], to defects located in the (Cdoped) buffer [6], or to the injection of electrons from the substrate [38]. These trapping processes are not specific for p-GaN gate devices, and their discussion is beyond the scope of this paper.…”
Section: Charge Trapping Processes Related To the P-gan Gatementioning
confidence: 97%
“…Time-to-failure (TTF) is defined as the time necessary for reaching a gate leakage of 10 mA (measured at 8.5 V). Electroluminescence measurements (Figure 10) indicate that each of the steps in gate current corresponds to the appearance of a "hot-spot", corresponding to the creation of As in the case of normally-off transistors, the exposure to high drain bias in the off-state can trigger further trapping processes, due to the filling of surface states [8], to defects located in the (C-doped) buffer [6], or to the injection of electrons from the substrate [38]. These trapping processes are not specific for p-GaN gate devices, and their discussion is beyond the scope of this paper.…”
Section: Degradation Processes Induced By Positive Gate Biasmentioning
confidence: 99%