Traveling-wave ring oscillator — a new architecture for a transmission line based oscillator

Likhterov, Boris; Belenky, A.

doi:10.1109/icsee.2016.7806048

Cited by 2 publications

(1 citation statement)

References 13 publications

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“…The theoretical analysis was verified not only by simulation results, but also physical measurement. In prior works, the measurement results were much worse than the post-layout simulation results mainly due to lack of layout style analysis [18]- [20], and the worst frequency drift is about 0.2 GHz from 1 GHz-3 GHz in these works. Notably, many prior digital circuit design reports never gave details of their clock or OSC generator layout, e.g., [21]- [24].…”

Section: Literature Surveymentioning

confidence: 96%

Analysis of Layout Arrangement for CMOS Oscillators to Reduce Overall Variation on Silicon

Lou¹,

Ho²,

Wang³

et al. 2022

Adv. sci. technol. eng. syst. j.

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This investigation demonstrates the analysis of various layout arrangements for oscillator (OSC) realized by CMOS technologies. Moreover, the analysis reveals that the serpentine style of OSC stages attains the minimum output variation on silicon. This investigation is firstly verified by post-layout simulations, comparing the variation with different kinds of layout arrangement for OSC designs, including serpentine layout style, straight layout style, and staggered layout style, etc. The proposed design is then realized using 0.18 µm process to justify the performance, where a straight line layout style and a serpentine layout style of OSC are physically fabricated on the same die. Besides, the on-silicon measurement is conducted to give the comparison for these two different styles of OSC designs. The proposed serpentine layout style attains the lowest layout variation when the variations are not homogeneous in different directions on the same silicon plane.

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