2008 Symposium on Application Specific Processors 2008
DOI: 10.1109/sasp.2008.4570794
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TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing

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Cited by 21 publications
(6 citation statements)
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“…Each core consists of 32 thread processors, and an L1 cache and some floating point function units shared within the core. As reported in [4] we estimate that in a 150mm square die we could instantiate 22 cores (704 thread processors) in a 130nm technology and 78 cores (2496 thread processors) in a 65nm technology using standard cell based implementations at a conservative 500MHz. Higher densities and speeds would be achievable with more use of custom circuits.…”
Section: Trax Architecturementioning
confidence: 87%
See 1 more Smart Citation
“…Each core consists of 32 thread processors, and an L1 cache and some floating point function units shared within the core. As reported in [4] we estimate that in a 150mm square die we could instantiate 22 cores (704 thread processors) in a 130nm technology and 78 cores (2496 thread processors) in a 65nm technology using standard cell based implementations at a conservative 500MHz. Higher densities and speeds would be achievable with more use of custom circuits.…”
Section: Trax Architecturementioning
confidence: 87%
“…The TRaX architecture is a multi-core chip architecture described in more detail in [4]. Our overall chip design is a die consisting of an L2 cache with an interface to off-chip memory and a number of repeated identical cores.…”
Section: Trax Architecturementioning
confidence: 99%
“…As SaarCOR and ray casting solutions, RPU also uses packet ray-tracing which can result in performance drops in the case of incoherent rays. The TRaX architecture [16] implements a different solutionmany identical cores consisting of simple thread processors. It can be viewed as general pur-pose architecture and is used in other papers to simu-late their hardware [7].…”
Section: Related Work In Ray Tracing Acceleration Hardwarementioning
confidence: 99%
“…Also [1] implements the idea of partitioning BVH into treelets (which approximately matches cache sizes) and group-ing rays according to treelets they intersect. Another architecture -STRaTA [7] is built on top of the TRaX [16] and implements modified treelet technique of [1] and streaming approach to processing rays associated with each treelet. STRaTA adds special small buffers to memory hierarchy to store rays.…”
Section: Related Work In Ray Tracing Acceleration Hardwarementioning
confidence: 99%
“…Ray tracing implementations on these architectures is accomplished through software kernels that then run on the processors. Other multicore architectures for ray tracing include SaarCore [20] [21], RPU [22] [23] and TRaX [24].…”
Section: B Graphics Hardwarementioning
confidence: 99%