2013
DOI: 10.1088/1748-0221/8/12/c12043
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TRB3: a 264 channel high precision TDC platform and its applications

Abstract: The TRB3 features four FPGA-based TDCs with < 20 ps RMS time precision between two channels and 256+4+4 channels in total. One central FPGA provides flexible trigger functionality and GbE connectivity including powerful slow control. We present recent users' applications of this platform following the COME&KISS principle: successful test beamtimes at CERN (CBM), in Jülich and Mainz with an FPGA-based discriminator board (PaDiWa), a charge-to-width FEE board with high dynamic range, read-out of t… Show more

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Cited by 81 publications
(76 citation statements)
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“…The outputs of every eight timing circuits are wired-or together (four channels/layer in total) and send to a FPGA based TDC with a time resolution of 20 ps. Further details on the data acquisition system based on the TRB3 platform can be found in [6,7]. The readout of the detector comprises twenty one charge sensing amplifiers and thirty two timing channels on the front end electronics side and twenty one ADC and four TDC channels on the DAQ side.…”
Section: Methodsmentioning
confidence: 99%
“…The outputs of every eight timing circuits are wired-or together (four channels/layer in total) and send to a FPGA based TDC with a time resolution of 20 ps. Further details on the data acquisition system based on the TRB3 platform can be found in [6,7]. The readout of the detector comprises twenty one charge sensing amplifiers and thirty two timing channels on the front end electronics side and twenty one ADC and four TDC channels on the DAQ side.…”
Section: Methodsmentioning
confidence: 99%
“…To that end, we are reading out well over 3000 TDC channels, and 500 ADC channels, which are used to monitor gains and provide event-by-event walk corrections to improve timing in the SPS, BH and BM. All TDC signals and scalars are provided by TRB3 read-out boards [25], which are each equipped with 5 FPGAs, four peripheral FPGAs which read out individual channels, and one central FPGA which manages triggering, data-flow, and synchronization. Each TDC channel has an accompanying scalar, built into the TRB3 infrastructure.…”
Section: Detector Electronics and Data Acquisition Systemmentioning
confidence: 99%
“…The input to the TRB3s comes from three different types of discriminator. The SPS is read out by PADIWA level discriminators, which are effective and inexpensive, designed by GSI to work with the TRB3 system [25]. The STTs faced large noise issues when they were first installed, and specially constructed PASTTREC cards were ordered, which have suppressed the noise issues, allowing the STTs to reach their designed resolution and efficiency [26].…”
Section: Detector Electronics and Data Acquisition Systemmentioning
confidence: 99%
“…The following prototype coined as FARICH-3 is based on multianode PMTs which are readout by PADIWA (amplifier-discriminator) and TRB3 (TDC DAQ platform) electronics developed for PANDA, CBM and HADES experiments at GSI [15].…”
Section: Farich Randd Progressmentioning
confidence: 99%