Trench storage node technology for gigabit DRAM generations

Müller, K.P.; Flietner, B.; Hwang, C.; Kleinhenz, R.; Nakao, T.; Ranade, R.M.; Tsunashima, Y.; Mii, T.

doi:10.1109/iedm.1996.553853

Cited by 24 publications

(9 citation statements)

References 2 publications

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“…The most promising candidate for realizing the simultaneous process is process technology with feature of trench etching of silicon substrate. The example of this process is shown in Fig.8 (A) [11]. Using small pattern size which is smaller than the feature size, F, various depth of trench can be successfully fabricated simultaneously with the optimization of trench etching process.…”

Section: Further Reduction Of Pattern Area and Chip Cost With Simultamentioning

confidence: 99%

Study of chip cost of LSI using FinFET with plural number of sidewall channel width

Yu¹,

Watanabe²

2013

ces

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Study of chip cost of LSI using FinFET with plural number of sidewall channel width is newly described. Using the sequential fabrication of 3-4 kinds of sidewall channel chip cost of buffer circuit and CMOS cell library can be reduced by 5-5.7% compared with of that with conventional single number of sidewall channel width. Further reduction of chip cost can be realized by using simultaneous fabrication process. LSI using FinFET with plural number of sidewall channel width is promising candidate for realizing low cost high density LSI. Furthermore, simultaneous process has the possibility to change the presently available CAD technology for LSI drastically.

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Section: Further Reduction Of Pattern Area and Chip Cost With Simultamentioning

confidence: 99%

Study of chip cost of LSI using FinFET with plural number of sidewall channel width

Yu¹,

Watanabe²

2013

ces

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“…The primary metrics considered in trench etching include a high etching rate even for ultrahigh-aspect-ratio features and control of trench taper angles to very tight limits. Figure 16 shows features of the trench capacitor used in the 256Mb DRAM chip developed by IBM, Siemens, and Toshiba [3,38]. After trench etching, the trench depth d is ~8 /u,m, comprising an upper portion of depth d, and a bottom portion of depth d^ In a top-down view, the trench is oval in shape, with a width w being 0.34 /am and a length / being 0.56 /j,m.…”

Section: Selective Dielectric Etchingmentioning

confidence: 99%

Plasma-etching processes for ULSI semiconductor circuits

et al. 1999

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“…After that trenches are formed for realizing vertically funning wires and silicon pillar for Fe-FET as shown in Fig.5(b). Trench depths are different as shown in the Figure. For realizing the different trench depths with one step of fabrication process different trench opening size scheme is employed[20] [21]. Next ferroelectric film is formed for the silicon pillar as shown in Fig.5(c).…”

Section: Introductionmentioning

confidence: 99%

Proposal of stacked type Fe-FET reconfigurable logic circuit featured with parallel processing within one silicon pillar using modified process technology of 3D NAND flash memory

Yokota¹,

Watanabe²

2018

ces

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In order to realize the parallel processing within one silicon pillar, a novel stacked type Fe-FET reconfigurable logic circuit featured with parallel processing within one silicon pillar using modified process technology of 3D NAND flash memory has been newly proposed. For realizing the proposed scheme plural numbers of logics are generated within one silicon pillar. Furthermore, the outputs of these logics are connected to horizontally running wires and these wires are connected to vertically running wires which act as the output signals. For realizing this structure two improvements for fabrication scheme of 3D NAND flash memory should be introduced. First is fabrication process featured by various depth trench formation technology with one fabrication step. Second is connection technology between the output of logic block generated within the silicon pillar to horizontal running wires.

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Trench storage node technology for gigabit DRAM generations

Cited by 24 publications

References 2 publications

Study of chip cost of LSI using FinFET with plural number of sidewall channel width

Study of chip cost of LSI using FinFET with plural number of sidewall channel width

Plasma-etching processes for ULSI semiconductor circuits

Proposal of stacked type Fe-FET reconfigurable logic circuit featured with parallel processing within one silicon pillar using modified process technology of 3D NAND flash memory

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