Trench superjunction VDMOS with charge imbalance cells

Sun, Weifeng; Zhu, Jun‐Jie; Qu, Qian; Cao, Ping; Liu, Siyang; Su, Zhan; Lu, Shengli; Shi, Longxing

doi:10.1016/j.sse.2011.07.006

Cited by 3 publications

(1 citation statement)

References 4 publications

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“…8 b shows the dependence of the BV and FOM on the top width of the P‐pillar. Since there is a charge balance between the P‐pillar and N‐Si‐pillar [20], the BV decreases with the increasing of charge mismatch. The on‐state conductive region and N‐pillar charge ( Q n estimated from the phosphorus concentration of the N epitaxial layer) decrease with the increasing of L , so the BV and FOM get the maximum value as L is 0.5 μm.…”

Section: Resultsmentioning

confidence: 99%

Split gate resurf stepped oxide UMOSFET with P‐pillar for improved performance

Wang

et al. 2014

IET Power Electronics

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In this work, the authors propose a split-gate resurf stepped oxide with P-pillar (SGRSOP) UMOS structure. The Ppillar trench under the source electrode in SGRSOP U-shape metal-oxide-semiconductor (UMOS) serves the purpose of simultaneously achieving the following: (1) it has formed a local super junction (SJ) structure with the N-type drift. The Ppillar modulates the electric field distribution in the local SJ and increases the N − drift region doping concentration. (2) It has suppressed the parasitic bipolar junction transistor (BJT) effect by adding the P-pillar in the N − drift region, enlarges the boundary of the snapback. As compared with the SGRSO UMOS, the SGRSOP UMOS only add the P-pillar structure, while it has the better performance. The simulation results show that the SGRSOP UMOS reduces the on-state specific resistance (R SP) and increases the transconductance (g m), improves the figure of merit and its UIS ruggedness is as good as that of the split-gate resurf stepped oxide UMOS.

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Section: Resultsmentioning

confidence: 99%