Trends for deep submicron VLSI and their implications for reliability

Chatterjee, P.K.; Hunter, W. R.; Amerasekera, A.; Aur, S.; Duvvury, C.; Nicollian, P.E.; Ting, Larry; Yang, Ping

doi:10.1109/relphy.1995.513645

Cited by 33 publications

(5 citation statements)

References 11 publications

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“…In fact, for these devices, market pressure has driven improvements in reliability for the devices. The failure rate of the devices has decreased from 320 FITs [1] in 1980 to below 32 FITs in 1990, and the downward trend is continuing (Chatterjee et al, 1995).…”

Section: Introductionmentioning

confidence: 99%

“…Subsequent BIR activities emerged first in manufacturing, then gravitated to productization, and then finally emerged as a major concern in R&D. We are now in the next wave of BIR, which is seeing knowledge from R&D having a greater influence on manufacturing. This is the result of recognizing that every flow-design feature has a corresponding strong or medium sensitivity in at least one reliability or robustness mechanism (Chatterjee et al, 1995). This means that a change in any of the common flow-design features will have an impact on reliability or robustness, which further emphasizes the need for BIR.…”

Section: Introductionmentioning

confidence: 99%

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Customer‐focused build‐in reliability: a case study

Tan

2003

International Journal of Quality &Amp; Reliability Management

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Build-in reliability (BIR) is becoming an essential requirement for product development today. However, the task of BIR can be resource-intensive since root causes identification is necessary. If a product is complex, the number of possible failure modes can be great, rendering BIR too large to be practical. In this work, an objective methodology for BIR is developed so that the task of BIR is customer focus, thus reducing the scope of BIR and maximizing its effectiveness. This is achieved through combining the failure mode and effect analysis (FMEA) with quality function deployment (QFD). The method is applied to an actual product in an actual industry, and with this method the FMEA becomes customer-focused, and hence the prioritization of the corrective actions to all failure modes can be done objectively with customer focus. Therefore, limited resources can be effectively used to maximize customers' satisfaction.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Customer‐focused build‐in reliability: a case study

Tan

2003

International Journal of Quality &Amp; Reliability Management

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“…However, gate oxide thickness must be scaled down to meet the device performance requirement and reduction trend. 3-nm oxide may be needed for the 0.1m generation [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Plasma charging damage on ultrathin gate oxides

Park

1998

IEEE Electron Device Lett.

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Capacitor C0V and threshold voltage and subthreshold swing of MOSFET's with gate oxide thickness varying from 2.2 to 7.7 nm are analyzed to study the plasma charging damage by the metal etching process. Surprisingly, the ultrathin gate oxide has better immunity to plasma charging damage than the thicker oxide, thanks to the excellent tolerance of the thin gate oxide to tunneling current. This finding has very positive implications for the prospect of manufacturable scaling of gate oxide to very thin thickness.Index Terms-Charging damage, diode protection, oxide scaling, reliability, thin gate oxide.

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“…However, with the rapid advancement of IC technologies, the wire width is reduced dramatically, whereas the operating voltage and current are not reduced at the same rate as IC physical dimensions [9,10]. Consequently, the current density in signal nets increases exponentially as the feature size scales downward [2]. In addition, high performance circuit families are aggressively exploited in modern IC designs and these circuits try to speed up one of signal transitions at the expense of the other.…”

Section: Introductionmentioning

confidence: 99%

Current Calculation on VLSI Signal Interconnects

Shao

Gao

Yuan

et al.

Sixth International Symposium on Quality of Electronic Design (ISQED'05)

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With IC technology scaling down to nanometer, the higher working frequency and smaller geometry drive the reliability of signal interconnects to be a critical challenge in VLSI design. The post-layout reliability verification is an effective solution to this challenge. However, the implementation of a full-chip verification on signal electromigration requires huge amounts of interconnect current calculation. The dynamic current calculation methods established on time domain circuit simulators are prohibitively expensive of runtime when applied to DSM ICs. Therefore, in this paper, we propose an efficient static current calculation technique. One of distinguished characteristics of this technique is that current calculations are based on ramp input signals, the more realistic signal than the step input. Moreover, an advanced gate model is applied to this technique, thus the current it yields is more accurate than that using switch-resistor model. Since different electromigration models require different types of interconnect current values in their evaluations, this technique can handle the calculation on average, RMS and peak current in order to perform a comprehensive reliability validation in IC designs. The experimental results demonstrate its efficiency and accuracy of this technique. Combined with the pruning technique, it is also integrated into a reliability verification flow to be tested on a SoC design.

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Trends for deep submicron VLSI and their implications for reliability

Cited by 33 publications

References 11 publications

Customer‐focused build‐in reliability: a case study

Customer‐focused build‐in reliability: a case study

Plasma charging damage on ultrathin gate oxides

Current Calculation on VLSI Signal Interconnects

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