Trends in bipolar static random access memory (SRAM) design

A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18-µm complementary-metal-oxide-semiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.

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Standing, Causation, and Remedies Under the Cartwright Act

Elias¹

2019

SSRN Journal

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Trends in bipolar static random access memory (SRAM) design

Cited by 3 publications

References 28 publications

SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance

SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance

New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance

Standing, Causation, and Remedies Under the Cartwright Act

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