Tri-State Nanoelectromechanical Memory Switches for the Implementation of a High-Impedance State

Abstract

Tri-state nanoelectromechanical (NEM) memory switches are proposed for the implementation of high-impedance state 0 in addition to low-impedance states 1 and 2 for the improvement of conventional complementary metal-oxide-semiconductor-NEM (CMOS-NEM) reconfigurable logic (RL) operations. Although it is well known that the high impedance state of routing switches is essential to prevent the unnecessary data throughput of RL circuits, previously proposed NEM memory switches have only implemented binary states: states 1 and 2. On the contrary, our proposed NEM memory switches can have tri-states, which are achieved by modifying their operation methods and design guidelines. INDEX TERMS High impedance, nanoelectromechanical (NEM) memory switch, reconfigurable logic (RL), tri-state operation.

Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch

“…They operate in the same manner as SRAMs in the write and read modes. For example, to store a '1' in a memory cell, a '1' In this study, three-dimensional integrated nanoelectromechanical (NEM) memory switches, which are driven by an electromechanical principle, are used in place of conventional CMOS transistors to overcome the limitations of CMOS-based CAMs and increase the density of the front-end area [25][26][27]. This work is an extension of [22], and is proposing a new CAM architecture with an advanced precharge circuit to improve stability in practical operation for both BCAM and TCAM by using a single NEM cell.…”

“…The NEM memory switch connects the path by controlling the central movable beam. A movable beam that has moved once is non-volatile, and maintains the path after writing the data, owing to the van der Waals adhesion force [25][26][27]. For example, when a sufficient voltage is applied to L 1 , the beam forms a path with L 1 , and when sufficient voltage is applied to L 2 , the beam forms a path to L 2 .…”

“…In this study, we used Cadence's Spectre simulation platform to perform the simulation, and we used Mentor Graphics' Calibre LVS and DRC verification software to verify the circuit design and layout. Moreover, the Verilog-A model was used for the proposed NEM memory switch [27].…”