Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced I&lt;inf&gt;on&lt;/inf&gt; and nearly defect-free channels

Hsu, Shu‐Han; Chang, Hung‐Chih; Chu, Chun-Lin; Chen, Yen‐Ting; Tu, Wen‐Hua; Hou, Fu-Ju; Lo, Chih Hung; Sung, Po-Jung; Chen, Bo‐Yuan; Huang, Guo-Wei; Luo, Guang-Li; C, Liu; Hu, Chenming; Yang, Fu-Liang

doi:10.1109/iedm.2012.6479090

Cited by 10 publications

(7 citation statements)

References 2 publications

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“…Planar, long channel Ge n-MOSFETs with optimized gate-stacks have shown D it of the order of 10 11 V −1 ·cm −2 , as measured by low-temperature conductance method [38]- [40]. While the I ON values measured in our Ge/Si 1-x Ge x NW n-FETs are comparable with those of short channel Ge n-FinFETs fabricated using top-down methods [12], [13], our data strongly suggested that these values can be significantly increased by using optimized gatestacks.…”

Section: Device Characterization and Scaling Propertiessupporting

confidence: 75%

“…4(a), which can be explained by the gate-induced drain leakage. These performance metrics are comparable with those of Ge n-FinFETs fabricated from epiGe grown directly on silicon-on-insulator [12], [13]. Unlike the reference device without a Si 1-x Ge x shell (Fig.…”

Section: Device Characterization and Scaling Propertiessupporting

confidence: 69%

“…Advanced architectures, such as tunneling FETs [6], [7] and multigate FETs [8], have been proposed to enhance the scalability of Ge-based devices. Indeed, recent studies have reported p-and n-type Ge FinFETs fabricated by top-down approaches [9]- [13], suggesting that Ge can serve as the material of choice for future logic devices.…”

Section: Introductionmentioning

confidence: 99%

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Realization and Scaling of ${\rm Ge}{\hbox{--}}{\rm Si}_{1{\hbox{-}}{\rm x}}{\rm Ge}_{\rm x}$ Core-Shell Nanowire $n$-FETs

Liu

Dillen

Nah

et al. 2013

IEEE Trans. Electron Devices

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We present the realization and scaling properties of germanium-silicon-germanium (Ge-Si 1-x Ge x ) core-shell nanowire (NW) n-type, -gate field-effect transistors (FETs). The devices show superior performance to the counterparts without the Si 1-x Ge x shell. With a channel length (L ch ) of 380 nm and a diameter of 40 nm, we demonstrate a subthreshold swing of 180 mV/dec, and an ON-current (I ON ) of 60 μA/μm, comparable with recent results in Ge n-type FinFETs fabricated by top-down techniques. By systematically studying the scaling properties, we identify the contribution of the channel and contact resistances to device characteristics. We conclude that I ON is not limited by the contact resistance but rather by a relatively large channel resistance, presumably associated with a high-interface trap density ( D i t ).

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Section: Device Characterization and Scaling Propertiessupporting

confidence: 75%

Section: Device Characterization and Scaling Propertiessupporting

confidence: 69%

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Realization and Scaling of ${\rm Ge}{\hbox{--}}{\rm Si}_{1{\hbox{-}}{\rm x}}{\rm Ge}_{\rm x}$ Core-Shell Nanowire $n$-FETs

Liu

Dillen

Nah

et al. 2013

IEEE Trans. Electron Devices

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“…Gate-all-around (GAA) is a widely adapted structure to fabricate the field-effect transistor with its excellent short channel characteristics and high surface-to-volume ratio. 13,14 Stacked gate-all-around nanosheet architectures are now gaining traction, particularly at sub-5 nm technological nodes. The GAA structures have superior electrostatics over the channel and stacking NWs/NSs boost the overall drive current while keeping the active area the same.…”

Section: Introductionmentioning

confidence: 99%

Demonstration of Monolayer Doping of Five-Stacked Ge Nanosheet Field-Effect Transistors

Chu

Luo

Chou

et al. 2022

ACS Appl. Electron. Mater.

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Monolayer doping (MLD) allows devices with complex-geometry structures like nanopillar arrays, nanofins, and nanosheets to be created. These are some of the devices that might be used in next-generation semiconductor technology. Horizontally stacked nanosheet gate-all-around field-effect transistors (GAA FETs), same as gate-all-around nanowire FETs (GAA NW-FETs) technology, have the capacity to extend the technology node down to 5 nm with a good short channel control, which is the current constraint of the existing FinFET. Low-dimensional Ge structures have also attracted a lot of interest with their superior electrical properties compared to standard Si devices. As a result, a fabrication scheme combining high-quality Ge/Si multilayer epitaxy, excellent selective etching control, crystallization by forming gas annealing, and conformal monolayer doping has been demonstrated, allowing for the formation of multilayer stacking of Ge nanosheet gate-all-around field-effect transistors (p-GAA FETs). The crystalline Ge nanosheet is characterized by transmission electron microscopy, and excellent electronic properties are demonstrated using boron-containing molecules for conformal doping to overcome the geometry limitation with two different gate length channels. These successful representations of GAA devices achieved by conformal monolayer doping methodologies can provide significant information for developing emerging three-dimensional (3D) integrated Ge nanodevices beyond a 5 nm generation node.

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“…In addition to characteristics such as high mobility, new device architectures such as those of gate-all-around (GAA) [ 2 ] and ultrathin-body field-effect transistors (FETs) [ 3 ] are needed to improve electrostatic control in the sub-10 nm nodes. Ge-based GAA pFETs [ 4 ] and nFETs [ 5 ] with inversion-mode (INV) operation have been demonstrated. However, junction formation in Ge INV devices is a critical issue owing to the low dopant solubility, rapid dopant diffusion, and low thermal budget.…”

Section: Introductionmentioning

confidence: 99%

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

2018

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During the formation of Ge fin structures on a silicon-on-insulator (SOI) substrate, we found that the dry etching process must be carefully controlled. Otherwise, it may lead to Ge over-etching or the formation of an undesirable Ge fin profile. If the etching process is not well controlled, the top Ge/SOI structure is etched away, and only the Si fin layer remains. In this case, the device exhibits abnormal characteristics. The etching process is emerging as a critical step in device scaling and packaging and affects attempts to increase the packing density and improve device performance. Therefore, it is suggested that optimization of operating the plasma reactor be performed through simulations, in order to not only adjust the process parameters used but also to modify the hardware employed. We are going to develop Ge junction-less devices by employing updated fabrication parameters. Besides, we want to eliminate misfit dislocations at the interface or to reduce threading dislocations by applying cyclic thermal annealing process to meet the goal of obtaining suspended structure of epitaxial Ge layers with high quality.

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Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced I<inf>on</inf> and nearly defect-free channels

Cited by 10 publications

References 2 publications

Realization and Scaling of ${\rm Ge}{\hbox{--}}{\rm Si}_{1{\hbox{-}}{\rm x}}{\rm Ge}_{\rm x}$ Core-Shell Nanowire $n$-FETs

Realization and Scaling of ${\rm Ge}{\hbox{--}}{\rm Si}_{1{\hbox{-}}{\rm x}}{\rm Ge}_{\rm x}$ Core-Shell Nanowire $n$-FETs

Demonstration of Monolayer Doping of Five-Stacked Ge Nanosheet Field-Effect Transistors

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

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