Triggering of Transient Latch-up by System-Level ESD

Brodbeck, T.; Stadler, Wolfgang; Baumann, C.; Esmark, K.; Domanski, K.

doi:10.1109/tdmr.2011.2165072

Cited by 10 publications

(1 citation statement)

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“…The influence of ambient temperature obtained here can be verified with Ref. [15], which concludes the latch-up triggering voltage decreases with temperature increasing from 300 to 400 K. The comparison of the two results is shown in Fig. 7 by a normalization method, with the triggering voltage at 300 K is used as a reference.…”

Section: Hpm Susceptibility Trend As a Function Of Ambient Temperaturesupporting

confidence: 81%

Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave

Yu¹,

Chai²,

Xingrong³

et al. 2014

J. Semicond.

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The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave (HPM) is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS inverters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.

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Section: Hpm Susceptibility Trend As a Function Of Ambient Temperaturesupporting

confidence: 81%